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參數(shù)資料
| 型號： | MAX11207EEE+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 20BIT 480SPS 16QSOP |
| 產品培訓模塊： | MAX11200 ADC Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 100 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 480 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 667mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-QSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
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18
Maxim Integrated
20-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
MAX11206/MAX11207
STAT1: Status Register
SYSOR: The system gain overrange bit, when set to 1, indicates that a system gain calibration was over range. The
SCGC calibration coefficient is maximum value of 1.9999999. This bit, when set to 1, indicates that the full-scale value
out of the converter is likely not available.
RATE[2:0]: The data rate bits indicate the conversion rate that corresponds to the result in the DATA register or the
rate that was used for calibration coefficient calculation. If the previous conversions were done at a different rate, the
RATE[2:0] bits indicate a rate different than the rate of the conversion in progress.
OR: The overrange bit, OR, is set to 1 to indicate the conversion result has exceeded the maximum value of the
converter and that the result has been clipped or limited to the maximum value. The OR bit is set to 0 to indicate the
conversion result is within the full-scale range of the device.
UR: The underrange bit, UR, is set to 1 to indicate the conversion result has exceeded the minimum value of the
converter and that the result has been clipped or limited to the minimum value. The UR bit is set to 0 to indicate the
conversion result is within the full-scale range of the device.
MSTAT: The measurement status bit, MSTAT is set to 1 when a signal measurement is in progress. When MSTAT = 1,
a conversion, self-calibration, or system calibration is in progress and indicates that the modulator is busy. When the
modulator is not converting, the MSTAT bit is set to 0.
RDY: The RDY ready bit is set to 1 to indicate that a conversion result is available. Reading the DATA register resets the
RDY bit to 0 only after another conversion has been initiated. If the DATA has not been read before another conversion
is initiated, the RDY bit remains 1; if the DATA is read before another conversion is initiated, the RDY bit resets to 0. If
the DATA for the previous conversion is read during a following conversion, the RDY bit is reset immediately after the
DATA read operation has completed.
Table 11. STAT1 Register (Read Only)
BIT
B7
B6
B5
B4
B3
B2
B1
B0
BIT NAME
SYSOR
RATE2
RATE1
RATE0
OR
UR
MSTAT
RDY
DEFAULT
0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX11207EEE+ | 功能描述:模數(shù)轉換器 - ADC 20-Bit Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX11207EEE+T | 功能描述:模數(shù)轉換器 - ADC 20-Bit Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX11208 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:20-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADC with 2-Wire Serial Interface |
| MAX11208AEUB+ | 功能描述:模數(shù)轉換器 - ADC 20-Bit Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX11208AEUB+T | 功能描述:模數(shù)轉換器 - ADC 20-Bit Delta-Sigma RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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