參數(shù)資料
型號： MAX1067AEEE
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： Multichannel, 14-Bit, 200ksps Analog-to-Digital Converters
中文描述： 4-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封裝： 0.150 INCH, 0.250 INCH PITCH, MO-137AB, QSOP-16
文件頁數(shù)： 5/30頁
文件大小： 447K
代理商： MAX1067AEEE
M
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= +4.75V to +5.25V, f
SCLK
= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external V
REF
= +4.096V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Shutdown Supply Current
I
AVDD
+
I
DVDD
CS
= DV
DD
, SCLK = 0, DIN = 0,
DSPR = DV
DD
, full power-down
0.6
10
μA
Power-Supply Rejection Ratio
PSRR
AV
DD
= DV
DD
= 4.75V to 5.25V, full-scale
input (Note 10)
63
dB
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)
(
AV
DD
= DV
DD
= +4.75V to +5.25V
, f
SCLK
= 4.8MHz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external V
REF
= +4.096V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
Acquisition Time
t
ACQ
External clock (Note 6)
SCLK to DOUT Valid
t
DO
C
DOUT
= 30pF
CS
Fall to DOUT Enable
t
DV
C
DOUT
= 30pF
CS
Rise to DOUT Disable
t
TR
C
DOUT
= 30pF
CS
Pulse Width
t
CSW
SCLK rise
CS
to SCLK Setup
t
CSS
SCLK fall (DSP)
SCLK rise
CS
to SCLK Hold
t
CSH
SCLK fall (DSP)
MIN
729
TYP
MAX
UNITS
ns
ns
ns
ns
ns
50
80
80
100
100
ns
0
ns
Conversion
Data transfer
Conversion
Data transfer
93
50
93
50
209
SCLK High Pulse Width
t
CH
Duty cycle 45% to 55%
ns
SCLK Low Pulse Width
t
CL
Duty cycle 45% to 55%
ns
SCLK Period
t
CP
ns
SCLK rise
SCLK fall (DSP)
SCLK rise
SCLK fall (DSP)
DIN to SCLK Setup
t
DS
50
ns
DIN to SCLK Hold
t
DH
0
ns
CS
Falling to DSPR Rising
DSPR to SCLK Falling Setup
DSPR to SCLK Falling Hold
t
DF
t
FSS
t
FSH
100
100
0
ns
ns
ns
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