參數(shù)資料
型號(hào): MAX1066BEUP+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 13/14頁(yè)
文件大?。?/td> 0K
描述: IC ADC 14BIT 165KSPS 20TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 14
采樣率(每秒): 165k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 16mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)單端,單極
MAX1065/MAX1066
Detailed Description
Converter Operation
The MAX1065/MAX1066 use a successive-approximation
(SAR) conversion technique with an inherent track-and-
hold (T/H) stage to convert an analog input into a 14-bit
digital output. Parallel outputs provide a high-speed inter-
face to most microprocessors (Ps). The
Functional
Diagram shows a simplified internal architecture of the
MAX1065/MAX1066. Figure 3 shows a typical application
circuit for the MAX1066.
Analog Input
The equivalent input circuit is shown in Figure 4. A
switched capacitor digital-to-analog converter (DAC)
provides an inherent track-and-hold function. The sin-
gle-ended input is connected between AIN and AGND.
Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid aliasing of
unwanted high-frequency signals into the frequency
band of interest, use antialias filtering.
Internal protection diodes, which clamp the analog
input to AVDD and/or AGND, allow the input to swing
from AGND - 0.3V to AVDD + 0.3V, without damaging
the device.
If the analog input exceeds 300mV beyond the sup-
plies, limit the input current to 10mA.
Track and Hold (T/H)
In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive DAC samples the analog input.
Low-Power, 14-Bit Analog-to-Digital Converters
with Parallel Interface
8
_______________________________________________________________________________________
CS
R/C
REF POWER-
DOWN BIT
EOC
D0–D13
HBEN*
DATA VALID
D7/D13–D0/D8*
HIGH/LOW
BYTE VALID
tACQ
tCONV
tCSH
tCSL
tDH
tDO
tDO1
tEOC
*HBEN AND BYTE-WIDE DATA BUS AVAILABLE ON MAX1066 ONLY.
tDS
tDV
HI–Z
HI-Z
HIGH/LOW
BYTE VALID
tBR
Figure 2. MAX1065/MAX1066 Timing Diagram
DGND
1mA
CLOAD = 20pF
D0–D13
CLOAD = 20pF
1mA
DGND
DVDD
a) HIGH-Z TO VOH,
VOL TO VOH, AND
VOH TO HIGH-Z
b) HIGH-Z TO VOL,
VOH TO VOL, AND
VOL TO HIGH-Z
Figure 1. Load Circuits for D0–D13 Enable Time, CS to D0–D13
Delay Time and Bus Relinquish Time
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