8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 14-Bit ADCs 24 Maxim Integrated E" />
參數(shù)資料
型號(hào)： MAX1033BEUP+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 17/32頁(yè)
文件大小： 0K
描述： IC ADC LP 4-CHAN 12V 20-TSSOP
標(biāo)準(zhǔn)包裝： 74
位數(shù)： 14
采樣率（每秒）： 115k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 105.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
輸入數(shù)目和類型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，雙極
MAX1032/MAX1033
8- and 4-Channel, ±3 x VREF
Multirange Inputs, Serial 14-Bit ADCs
24
Maxim Integrated
External Acquisition Mode (Mode 1)
The slowest maximum throughput rate is achieved with
the external acquisition method. SCLK controls the acqui-
sition of the analog signal in external acquisition mode,
facilitating precise control over when the analog signal is
captured. The internal clock controls the conversion of
the analog input voltage. The analog input sampling
instant is at the falling edge of the 16th SCLK (Figure 3).
For the external acquisition mode, CS must remain low
for the first 15 clock cycles and then rise on or after the
falling edge of the 16th clock cycle as shown in Figure
3. For optimal performance, idle DIN and SCLK during
the conversion. With careful board layout, transitions at
DIN and SCLK during the conversion have a minimal
impact on the conversion result.
After the conversion is complete, SSTRB asserts high
and CS can be brought low to read the conversion
result. SSTRB returns low on the rising SCLK edge of
the subsequent start bit.
Internal Clock Mode (Mode 2)
In internal clock mode, the internal clock controls both
acquisition and conversion of the analog signal. The inter-
nal clock starts approximately 100ns to 400ns after the
falling edge of the eighth SCLK and has a rate of about
4.5MHz. The analog input sampling instant occurs at the
falling edge of the 11th internal clock signal (Figure 4).
For the internal clock mode, CS must remain low for the
first seven SCLK cycles and then rise on or after the
falling edge of the eighth SCLK cycle. After the conver-
sion is complete, SSTRB asserts high and CS can be
brought low to read the conversion result. SSTRB returns
low on the rising SCLK edge of the subsequent start bit.
Reset (Mode 4)
As shown in Table 8, set M[2:0] = 100 to reset the
MAX1032/MAX1033 to its default conditions. The default
conditions are full power operation with each channel
configured for ±3 x VREF, bipolar, single-ended conver-
sions using external clock mode (mode 0).
Partial Power-Down Mode (Mode 6)
As shown in Table 8, when M[2:0] = 110, the device
enters partial power-down mode. In partial power-
down, all analog portions of the device are powered
down except for the reference voltage generator and
bias supplies.
To exit partial power-down, change the mode by issu-
ing one of the following mode-control bytes (see the
Mode Control section):
External-Clock-Mode Control Byte
External-Acquisition-Mode Control Byte
Internal-Clock-Mode Control Byte
Reset Byte
Full Power-Down-Mode Control Byte
This prevents the MAX1032/MAX1033 from inadvertent-
ly exiting partial power-down mode because of a CS
glitch in a noisy digital environment.
Full Power-Down Mode (Mode 7)
When M[2:0] = 111, the device enters full power-down
mode and the total supply current falls to 1μA (typ). In
full power-down, all analog portions of the device are
powered down. When using the internal reference,
upon exiting full power-down mode, allow 10ms for the
internal reference voltage to stabilize prior to initiating a
conversion.
To exit full power-down, change the mode by issuing
one of the following mode-control bytes (see the
Mode
Control section):
External-Clock-Mode Control Byte
External-Acquisition-Mode Control Byte
Internal-Clock-Mode Control Byte
Reset Byte
Partial Power-Down-Mode Control Byte
M2
M1
M0
MODE
0
External Clock (DEFAULT)
0
1
External Acquisition
0
1
0
Internal Clock
0
1
Reserved
1
0
Reset
1
0
1
Reserved
1
0
Partial Power-Down
1
Full Power-Down
Table 8. Mode-Control Bits M[2:0]
相關(guān)PDF資料
PDF描述
V48A48T500B CONVERTER MOD DC/DC 48V 500W
D38999/26WD97PC CONN PLUG 12POS STRAIGHT W/PINS
VE-J24-MX-F4 CONVERTER MOD DC/DC 48V 75W
ICL3241CBZ IC 3DRVR/5RCVR RS232 3V 28-SOIC
ICL3241IAZ IC 3DRVR/5RCVR RS232 3V 28-SSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX1033BEUP/GG8 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1033BEUP/GH9 制造商:Maxim Integrated Products 功能描述:8- AND 4-CHANNEL, +/-3 X VREF MULTIRANGE INPUTS, SERIAL 14-B - Rail/Tube
MAX1033BEUP+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 4Ch +/-12V Multi Inputs Serial 14-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1033BEUP+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 4Ch +/-12V Multi Inputs Serial 14-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1033EUP 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-/4-Channel, 【12V Multirange Inputs, Serial 14-Bit ADCs
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*