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參數(shù)資料
| 型號(hào)： | MAQ2901FD |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | RADIATION HARD 4-BIT MICROPROCESSOR SLICE |
| 中文描述： | 輻射硬4位微處理器切片 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 261K |
| 代理商： | MAQ2901FD |
MA2901
8
AC ELECTRICAL CHARACTERISTICS
Read-Modify-Write Cycle (from selection of A,B registers to end of a cycle
Maximum Clock Frequency to shift Q(50% duty cycle, I = 432 or 632)
Minimum Clock LOW time
Minimum Clock HIGH time
Minimum Clock Period
Note: 1. These timings are applied during functional tests and are not routinely measured.
40ns
25MHz
20ns
20ns
40ns
Figure 12: Cycle Time and Clock Characteristics
To Output
From Input
Y
F
3
C
n
+ 4
G,P
F = 0
OVR
RAM
0
RAM
3
65
55
50
65
65
30
-
55
Q
0
Q
3
-
-
-
-
-
30
-
35
A,B Address
D
C
n
I
0,1,2
I
3,4,5
I
6,7,8
A Bypass ALU(I=2xx)
Clock
Note: All timings in ns
65
55
60
70
60
45
45
55
55
40
40
50
45
-
-
50
60
50
35
55
50
-
-
55
55
50
-
55
45
-
-
50
70
65
55
70
65
-
-
50
65
55
35
55
50
-
-
55
Figure 13: Combinational Propagation Delays
Input
CP:
Set-up Time
Before H
→
L
25
25
-
-
-
-
10
-
Hold Time
After H
→
L
5
No change
-
-
-
-
No change
-
Set-up Time
Before L
→
H
30
No change
40
40
45
45
No change
15
Hold Time
After L
→
H
-
5
0
0
0
0
10
10
A,B Source Address
B Destination Address
D
C
n
I
0,1,2
I
3,4,5
I
6,7,8
RAM
0,3,
Q
0,3
MIL-STD-883, method 5005, subgroups 9, 10, 11
Note:
1. VDD = 5V
±
10%, over full operational temperature range
2. CL = 5
0
pF
Figure 14: Set-up and Hold Times Relative to Clock (CP) Input
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相關(guān)代理商/技術(shù)參數(shù) |
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