- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄102744 > MAH28151CXXXX (DYNEX SEMICONDUCTOR LTD) 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, CDIP28 PDF資料下載
參數(shù)資料
| 型號： | MAH28151CXXXX |
| 廠商： | DYNEX SEMICONDUCTOR LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 2/22頁 |
| 文件大小： | 220K |
| 代理商： | MAH28151CXXXX |
MA28151
10/22
3.12 STATUS READ DEFINITION
In data communication systems it is often necessary to
examine the status of the active device to ascertain if errors
have occurred or other conditions that require the processor’s
attention. The MA28151 has facilities that allow the
programmer to read the status of the device at any time during
the functional operation. (Status update is inhibited during
status read).
A normal read command is issued by the CPU with CDN
high to accomplish this function.
Some of the bits in the Status Read Format have identical
meanings to external output pins so that the MA28151 can be
used in a completely polled or interrupt-driven environment.
TxRDY is an exception.
Note that status update can have a maximum delay of 28
clock periods from the actual event affecting the status.
3.13 STATUS READ FORMAT
D
7
DSR
D
6
SYNDET
BRKDET
D
5
FE
D
4
OE
D
3
PE
D
2
Tx
EMPTY
D
1
RxRDY
D
0
TxRDY
PARITY ERROR
The PE flag is set when the
parity error is detected. It is
reset by the ER bit of the
Command Instruction. PE does
not inhibit the operation of the
MA28151.
Note 1: TxRDY status bit has different meanings from the TxRDY output pin. The former
is not conditioned by CTS and TxEN, the latter is conditioned by both CTS and TxEN.
ie. TxRDY status bit 0 DB buffer empty
TxRDY pin out = DB buffer empty OR (CTSN = 0) OR (TxEN = 1)
Note 1
Same as I/O pins
OVERRUN ERROR
The OE flag is set when the
CPU does not read a character
before the next one becomes
available. It is reset by the ER
bit of the Command Instruction
OE does not inhibit operation
of the MA28151, however the
previously overrun character is
lost.
FRAMING ERROR (ASYNC
ONLY)
The FE flag is set when a valid
Stop bit is not detected at the
end of every character. It is
reset by the ER bit of the
Command Instruction. FE does
not inhibit the operation of the
MA28151.
DATA SET READY
Indicates that the DSR is at a
zero level.
Figure 13: Status Read Format
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAQ28155CXXXX | 24 I/O, PIA-GENERAL PURPOSE, CDIP40 |
| M38037M6H-XXXHP | 8-BIT, MROM, 16.8 MHz, MICROCONTROLLER, PQFP64 |
| M30622M6P-XXXGP | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP100 |
| M32170F6VWG | 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PBGA255 |
| M37544G2SP | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAH28FAA | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 5.0 or 3.3 Volt, ACMOS/TTL, Clock Oscillators |
| MAH28FAA-R | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 5.0 or 3.3 Volt, ACMOS/TTL, Clock Oscillators |
| MAH28FAD | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 5.0 or 3.3 Volt, ACMOS/TTL, Clock Oscillators |
| MAH28FAD-R | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 5.0 or 3.3 Volt, ACMOS/TTL, Clock Oscillators |
| MAH28FAG | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:8 pin DIP, 5.0 or 3.3 Volt, ACMOS/TTL, Clock Oscillators |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。