參數(shù)資料
          型號: MAC7131VFU50
          廠商: 飛思卡爾半導體(中國)有限公司
          英文描述: Microcontroller Family Hardware Specifications
          中文描述: 微控制器系列硬件規(guī)格
          文件頁數(shù): 24/56頁
          文件大小: 471K
          代理商: MAC7131VFU50
          MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
          Preliminary
          Electrical Characteristics
          Freescale Semiconductor
          24
          3.10 Analog-to-Digital Converter
          Table 26
          and
          Table 27
          show conditions under which the ATD operates. The following constraints exist to
          obtain full-scale, full range results: V
          SS
          A
          V
          RL
          V
          IN
          V
          RH
          V
          DD
          A. This constraint exists because the
          sample buffer amplifier cannot drive beyond the ATD power supply levels. If the input level goes outside of
          this range it will effectively be clipped.
          Table 26. ATD Operating Characteristics in 5.0 V Range
          Conditions shown in
          Table 7
          unless otherwise noted
          Num C
          Rating
          Symbol
          Min
          Typ
          Max
          Unit
          N1
          D Reference Potential
          Low
          High
          V
          RL
          V
          RH
          V
          SS
          A
          V
          DD
          A
          ÷
          2
          V
          DD
          A
          ÷
          2
          V
          DD
          A
          V
          V
          N2
          C Differential Reference Voltage
          1
          NOTES:
          1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V
          2. Minimum time assumes a sample period of 2 ATD clocks; maximum time assumes a sample period of 16 ATD clocks.
          V
          RH
          – V
          RL
          4.50
          5.00
          5.50
          V
          N3
          D ATD Clock Frequency
          f
          ATDCLK
          0.5
          2.0
          MHz
          N4
          D ATD 10-bit Conversion Period
          f
          ATDCLK
          Cycles
          2
          @ 2.0MHz
          f
          ATDCLK
          N
          CONV10
          T
          CONV10
          14
          7
          28
          14
          Cycles
          μ
          s
          N5
          D ATD 8-bit Conversion Period
          f
          ATDCLK
          Cycles
          2
          @ 2.0MHz
          f
          ATDCLK
          N
          CONV8
          T
          CONV8
          12
          6
          26
          13
          Cycles
          μ
          s
          N6
          D Stop Recovery Time (V
          DD
          A = 5.0 V)
          T
          REC
          20
          μ
          s
          N7
          P Reference Supply current 1 ATD module on
          I
          REF
          0.200
          0.255
          mA
          N8
          P Reference Supply current 2 ATD modules on
          I
          REF
          0.400
          0.510
          mA
          Table 27. ATD Operating Characteristics in 3.3 V Range
          Conditions shown in
          Table 7
          , with V
          DD
          X = 3.3 V –5/+10% and a temperature maximum of +140
          °
          C unless otherwise
          noted.
          Num C
          Rating
          Symbol
          Min
          Typ
          Max
          Unit
          P1
          D Reference Potential
          Low
          High
          V
          RL
          V
          RH
          V
          SS
          A
          V
          DD
          A
          ÷
          2
          V
          DD
          A
          ÷
          2
          V
          DD
          A
          V
          V
          P2
          C Differential Reference Voltage
          1
          NOTES:
          1. Full accuracy is not guaranteed when differential voltage is less than 3.15 V
          2. Minimum time assumes a sample period of 2 ATD clocks; maximum time assumes a sample period of 16 ATD clocks.
          V
          RH
          – V
          RL
          3.15
          3.3
          3.6
          V
          P3
          D ATD Clock Frequency
          f
          ATDCLK
          0.5
          2.0
          MHz
          P4
          D ATD 10-bit Conversion Period
          f
          ATDCLK
          Cycles
          2
          @ 2.0MHz
          f
          ATDCLK
          N
          CONV10
          T
          CONV10
          14
          7
          28
          14
          Cycles
          μ
          s
          P5
          D ATD 8-bit Conversion Period
          f
          ATDCLK
          Cycles
          2
          @ 2.0MHz
          f
          ATDCLK
          N
          CONV8
          T
          CONV8
          12
          6
          26
          13
          Cycles
          μ
          s
          P6
          D Stop Recovery Time (V
          DD
          A = 3.3 V)
          T
          REC
          20
          μ
          s
          P7
          P Reference Supply current 1 ATD module on
          I
          REF
          0.130
          0.170
          mA
          P8
          P Reference Supply current 2 ATD modules on
          I
          REF
          0.260
          0.340
          mA
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