參數(shù)資料
型號(hào)： MAC7101CPV50
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Microcontroller Family Hardware Specifications
中文描述： 微控制器系列硬件規(guī)格
文件頁(yè)數(shù)： 29/56頁(yè)
文件大?。?/td> 471K
代理商： MAC7101CPV50
Electrical Characteristics
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
29
3.11 Serial Peripheral Interface
3.11.1 Master Mode
Master mode timing values are shown in
Table 32
and illustrated in
Figure 11
and
Figure 12
.
3.11.2 Slave Mode
Slave mode timing values are shown in
Table 33
and illustrated in
Figure 13
and
Figure 14
.
Table 32. SPI Master Mode Timing Characteristics
Conditions are shown in
Table 7
unless otherwise noted, C
LOAD
= 200 pF on all outputs
Num C
Rating
Symbol
f
OP
1
Min
Typ
Max
2
Unit
U1a
P Operating Frequency (baud rate)
NOTES:
1. Refer to
MAC7100 Microcontroller Family Reference Manual
(MAC7100RM) Chapter 22 for all available baud rates.
2. On mask set L49P and L47W devices,
U1a
maximum = and
U1b
minimum = 4.
—
f
IPS
U1b
U2
U3
U4
U5
U6
U9
U10
U11
U12
P SCK Period (t
SCK
= 1
÷
f
OP
, t
IPS
= 1
÷
f
IPS
)
D Enable Lead Time
D Enable Lag Time
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Data Valid (after Enable Edge)
D Data Hold Time (Outputs)
D Rise Time Inputs and Outputs
D Fall Time Inputs and Outputs
t
SCK
1
t
lead
t
lag
t
wsck
t
su
t
hi
t
v
t
ho
t
r
t
f
2
2
—
—
—
—
—
—
—
—
—
—
7
×
32,768
—
—
1024 t
IPS
—
—
25
—
25
25
t
IPS
t
SCK
t
SCK
ns
ns
ns
ns
ns
ns
ns
t
IPS
30
25
0
—
0
—
—
Table 33. SPI Slave Mode Timing Characteristics
Conditions are shown in
Table 7
unless otherwise noted, C
LOAD
= 200 pF on all outputs
Num C
Rating
Symbol
Min
32 678
Typ
Max
1
Unit
V1a
P Operating Frequency
f
OP
—
NOTES:
1. On mask set L49P and L47W devices,
V1a
maximum = and
V1b
minimum = 4.
f
IPS
V1b
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
P SCK Period (t
SCK
= 1
÷
f
OP
, t
IPS
= 1
÷
f
IPS
)
D Enable Lead Time
D Enable Lag Time
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Slave Access Time
D Slave SIN Disable Time
D Data Valid (after SCK Edge)
D Data Hold Time (Outputs)
D Rise Time Inputs and Outputs
D Fall Time Inputs and Outputs
t
SCK
t
lead
t
lag
t
wsck
t
su
t
hi
t
a
t
dis
t
v
t
ho
t
r
t
f
2
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
7
×
32,768
—
—
—
—
—
1
1
25
—
25
25
t
IPS
t
IPS
t
IPS
ns
ns
ns
t
IPS
t
IPS
ns
ns
ns
ns
t
IPS
30
25
25
—
—
—
0
—
—
----------------------------
7
×
----------------------------
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