參數(shù)資料
型號(hào): M7020R
廠商: 意法半導(dǎo)體
英文描述: 32K x 68-bit Entry NETWORK SEARCH ENGINE
中文描述: 32K的× 68位進(jìn)入網(wǎng)絡(luò)搜索引擎
文件頁(yè)數(shù): 92/150頁(yè)
文件大?。?/td> 996K
代理商: M7020R
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)當(dāng)前第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)
M7020R
92/150
272-bit SEARCH on Tables x272-configured Using Up to Eight M7020R Devices
The hardware diagram of the search subsystem of
eight devices is shown in Figure 66, page 94. The
following are the parameters programmed in the
eight devices.
– First seven devices (devices 0–6):
CFG = 10101010, TLSZ = 01, HLAT = 000,
LRAM = 0, and LDEV = 0.
– Eighth device (device 7):
CFG = 10101010, TLSZ = 01, HLAT = 000,
LRAM = 1, and LDEV = 1.
Note:
All eight devices must be programmed with
the same value of TLSZ and HLAT. Only the last
device in the table must be programmed with
LRAM = 1 and LDEV = 1 (Device 7 in this case).
All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (Devices 0 through
6 in this case).
Figure 68, page 96 shows the timing diagram for a
SEARCH command in the 272-bit-configured ta-
ble of eight devices for Device 0. Figure 69, page
97 shows the timing diagram for a SEARCH com-
mand in the 272-bit-configured table of eight de-
vices for Device 1. Figure 70, page 98 shows the
timing diagram for a SEARCH command in the
272-bit-configured table of eight devices for De-
vice 7 (the last device in this specific table). For
these timing diagrams three 272-bit searches are
performed sequentially. The following HIT/MISS
assumptions were made as shown in Table 43,
page 93.
The following is the sequence of operation for a
single 272-bit SEARCH command (also COM-
MAND CODES AND PARAMETERS, page 29).
Cycle A:
The host ASIC drives the CMDV high
and applies SEARCH command code ('10') on
CMD[1:0] signals. CMD[5:3] signals must be
driven with the index to the GMR pair used for
bits [271:136] of the data being searched in this
operation. DQ[67:0] must be driven with the 68-
bit data ([271:204]) to be compared against all
locations “0” in the four-word, 68-bit page. The
CMD[2] signal must be driven to logic '1.'
Note:
CMD[2] = 1 signals that the search is a
272-bit search. CMD[8:3] in this cycle is ig-
nored.
Cycle B:
The host ASIC continues to drive the
CMDV high and applies SEARCH command
code ('10') on CMD[1:0]. The DQ[67:0] is driven
with the 68-bit data ([203:136]) to be compared
against all locations “1” in the four 68-bits-word
page.
Cycle C:
The host ASIC drives the CMDV high
and applies SEARCH command code ('10') on
CMD[1:0] signals. CMD[5:3] signals must be
driven with the index to the GMR pair used for
bits [135:0] of the data being searched.
CMD[8:7] signals must be driven with the bits
that will be driven on SADR[21:20] by this de-
vice if it has a hit. DQ[67:0] must be driven with
the 68-bit data ([135:68]) to be compared
against all locations “2” in the four 68-bits-word
page. The CMD[2] signal must be driven to logic
'0.'
Cycle D:
The host ASIC continues to drive the
CMDV high and applies SEARCH command
code ('10') on CMD[1:0]. CMD[8:6] signals must
be driven with the index of the SSR that will be
used for storing the address of the matching en-
try and the Hit Flag (see SEARCH-Successful
Registers (SSR[0:7]), page 23). The DQ[67:0] is
driven with the 68-bit data ([67:0]) to be com-
pared to all locations “3” in the four 68-bits-word
page. CMD[5:2] is ignored because the LEARN
Instruction is not supported for x272 tables.
Note:
For 272-bit searches, the host ASIC must
supply four distinct 68-bit data words on
DQ[67:0] during Cycles A, B, C, and D. The
GMR Index in Cycle A selects a pair of GMRs in
each of the eight devices that apply to DQ data
in Cycles A and B. The GMR Index in Cycle C
selects a pair of GMRs in each of the eight de-
vices that apply to DQ data in Cycles C and D.
The logical 272-bit SEARCH operation is shown in
Figure 67, page 95. The entire table of 272-bit en-
tries is compared to a 272-bit word K that is pre-
sented on the DQ Bus in Cycles A, B, C, and D of
the command using the GMR and the local mask
bits. The GMR is the 272-bit word specified by the
two pairs of GMRs selected by the GMR Indexes
in the command’s Cycles A and C in each of the
eight devices. The 272-bit word K that is presented
on the DQ Bus in Cycles A, B, C, and D of the com-
mand is compared to each entry in the table start-
ing at location “0.” The first matching entry’s
location address, “L,” is the winning address that is
driven as part of the SRAM address on the
SADR[23:0] lines (see SRAM ADDRESSING,
page 126).
Note:
The matching address is always going to be
a location “0” in a four-entry page for 272-bit
SEARCH (two LSBs of the matching index will be
'00').
相關(guān)PDF資料
PDF描述
M72DW64000B 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product
M72DW64000B70ZT 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product
M72DW64000B90ZT 64Mbit (x8/ x16, Multiple Bank, Boot Block) Flash Memory and 16Mbit Pseudo SRAM, 3V Supply, Multiple Memory Product
M74AC574TTR OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING
M74AC574MTR OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M7020R-050ZA1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32K x 68-bit Entry NETWORK SEARCH ENGINE
M7020R-066ZA1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32K x 68-bit Entry NETWORK SEARCH ENGINE
M7020R-083ZA1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32K x 68-bit Entry NETWORK SEARCH ENGINE
M702-230442 功能描述:火線接頭 IEEE 1394 SMT 4P HORIZONTAL RoHS:否 制造商:Molex 產(chǎn)品:IEEE 1394 Firewire Connectors 標(biāo)準(zhǔn):IEEE 1394 位置/觸點(diǎn)數(shù)量:6 節(jié)距:2 mm 觸點(diǎn)電鍍:Unplated 觸點(diǎn)材料:Phosphor Bronze 型式:Female 電流額定值:0.5 A 安裝風(fēng)格:Through Hole 端接類型:Solder Tab 連接器類型:Firewire Receptacle
M702-230642 功能描述:火線接頭 IEEE 1394 SMT 6P HORIZONTAL RoHS:否 制造商:Molex 產(chǎn)品:IEEE 1394 Firewire Connectors 標(biāo)準(zhǔn):IEEE 1394 位置/觸點(diǎn)數(shù)量:6 節(jié)距:2 mm 觸點(diǎn)電鍍:Unplated 觸點(diǎn)材料:Phosphor Bronze 型式:Female 電流額定值:0.5 A 安裝風(fēng)格:Through Hole 端接類型:Solder Tab 連接器類型:Firewire Receptacle