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參數(shù)資料
| 型號： | M6MGT166S4BWG |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Series RC1083 rocker switches rated to 15 amp and snap-in panel mount |
| 中文描述： | 3.3的CMOS只快閃記憶體 |
| 文件頁數(shù)： | 24/30頁 |
| 文件大小： | 259K |
| 代理商： | M6MGT166S4BWG |
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Apr. 1999 , Rev.1.7
MITSUBISHI LSIs
16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS
3.3V-ONLY FLASH MEMORY &
4,194,304-BIT (262,144-WORD BY 16-BIT) CMOS SRAM
Stacked-CSP (Chip Scale Package)
M6MGB/T166S4BWG
24
When setting S-LB# at the high level and other pins are in
an active stage, upper-byte are in selectable mode in which
both reading and writing are enabled, and lower-byte are in
non-selectable mode. And when setting S-UB# at a high
level and other pins are in an active stage, lower-byte are in
a selectable mode and upper-byte are in a non-selectable
mode.
at high level or S-CE2 at a low level, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by S-LB#,S-UB# and S-CE1#,S-CE2.
The power supply current is reduced as low as
0.3
μ
A(25
°
C,typical), and the memory data can be held at
+2V powersupply, enabling battery back-up operation during
power failure or power-down operation in the non-selected
mode.
The SRAM of M6MGB/T166S4BWG is organized as
262,144-word by 16-bit. These devices operate on a single
+2.7~3.6V powersupply, and are directly TTL compatible to both
input and output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
The operation mode are determined by a combination of the
device control inputs , S-LB#,S-UB#,S-CE1#,S-CE2, S-WE#
and S-OE#. Each mode is summarized in the function table. When setting S-LB# and S-UB# at a high level or S-CE1#
A write operation is executed whenever the low level S-WE#
overlaps with the low level S-LB# and/or S-UB# and the low
level S-CE1#the high level S-CE2. The address A0~A16,SA-17
must be set up before the write cycle and must be stable during
the entire cycle.
A read operation is executed by setting S-WE# at a high level
and S-OE# at a low level while S-LB# and/or S-UB# and
S-CE1# and S-CE2 are in an active state(S-CE1#=L,S-CE2=H).
FUNCTION TABLE
Mode
S-WE#
X
High-Z
High-Z
High-Z
High-Z
S-OE#
X
DQ0~7
Non selection
S-UB#
X
Icc
Standby
Standby
Standby
Standby
DQ8~15
S-LB#
X
S-CE2
L
S-CE1#
H
L
H
X
L
Din
Dout
High-Z
High-Z
Read
Write
Active
Active
Active
Active
L
L
L
L
High-Z
High-Z
Din
Dout
Read
High-Z
Write
Active
Active
Active
L
L
L
L
L
H
X
H
H
H
H
H
H
H
H
H
X
X
H
L
L
L
H
H
H
L
L
L
X
X
H
H
H
H
L
L
L
L
L
L
X
X
X
L
H
H
L
H
H
L
H
H
X
X
X
X
L
H
X
L
H
X
L
H
Non selection
Non selection
Non selection
Read
Write
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Din
Dout
High-Z
Din
Dout
High-Z
Active
Active
2. SRAM
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