參數(shù)資料
型號: M68HC705UGANG
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
中文描述: 高密度互補金屬氧化物半導體(HCMOS)微控制器
文件頁數(shù): 49/112頁
文件大小: 809K
代理商: M68HC705UGANG
MC68HC05BD3
7-3
M-BUS SERIAL INTERFACE
7
7.2.1
START Signal
When the bus is free, i.e., no master device is occupying the bus (both SCL and SDA lines are at
logic high), a master may initiate communication by sending a START signal. As shown in
Figure 7-2, a START signal is defined as a high to low transition of SDA while SCL is high. This
signal denotes the beginning of a new data transfer (each data transfer may contain several bytes
of data) and wakes up all slaves.
7.2.2
Slave Address Transmission
The first byte of data transfer immediately following the START signal is the slave address
transmitted by the master. This is a seven bits long calling address followed by a R/W bit. The R/W
bit dictates the slave of the desired direction of data transfer.
Only the slave with matched address will respond by sending back an acknowledge bit by pulling
the SDA low at the 9th clock; see Figure 7-2.
Figure 7-2
M-Bus Transmission Signal Diagram
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
1
1
SCL
SDA
SCL
SDA
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Acknowledge bit
No acknowledge
START signal
STOP signal
repeated START signal
START signal
STOP signal
Acknowledge bit
No acknowledge
TPG
47
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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