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參數(shù)資料
| 型號： | M68AW031AM70NS1T |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 70 ns, PDSO28 |
| 封裝： | 8 X 13.40 MM, PLASTIC, REVERSE, TSOP-28 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 398K |
| 代理商： | M68AW031AM70NS1T |
Obsolete
Product(s)
- Obsolete
Product(s)
15/21
M68AW031A
Figure 14. Low VCC Data Retention AC Waveforms
Table 9. Low VCC Data Retention Characteristics
Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤ 0.2V.
2. Tested initially and after any design or process changes that may affect these parameters. tAVAV is Read cycle time.
3. No input may exceed VCC +0.2V.
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
ICCDR
(1)
Supply Current (Data Retention)
VCC = 1.5V, E ≥ VCC –0.2V, f = 0
(3)
6A
tCDR
(1,2)
Chip Deselected to Data
Retention Time
0ns
tR
(2)
Operation Recovery Time
tAVAV
ns
VDR
(1)
Supply Voltage (Data Retention)
E
≥ VCC –0.2V, f = 0
1.5
V
AI05905
DATA RETENTION MODE
tR
3.6V
tCDR
VCC
2.7V
VDR > 1.5V
E
≥ VDR – 0.2V
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