參數(shù)資料
型號(hào): M62320FP
廠商: Mitsubishi Electric Corporation
英文描述: 8-BIT I/O EXPANDER for I2C BUS
中文描述: 8位I / O擴(kuò)展I2C總線
文件頁數(shù): 8/9頁
文件大小: 66K
代理商: M62320FP
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
8-BIT I/O EXPANDER for I
C BUS
2/20,1998(rev) ( / 9 )
MITSUBISHI ELECTRIC
2
In case the I/O setting is different between each terminals.
An example : the parallel port terminals of D0 to D3 and D4 to D7 are assigned as output and input terminals,
respectively.
The input data is taken into the input latch on every 8th negative-going edge of the SCL clock through the
terminal assigned as an input, and then the latched data is output via the SDA line.
The data of the output assigned terminal is also handled in the same procedures as above.
D0 to D3
D
1
X
D
2
X
SCL
SDA
0
1
1
1
A2 A1 A0 0
A
P7 P6 P5 P4 P3 P2 P1 P0 A D
1
7D
1
6D
1
5D
1
4 D
1
3D
1
2D
1
1D
1
0 A D
2
7D
2
6D
2
5D
2
4 D
2
3D
2
2D
2
1D
2
0 A
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
DATA
DATA
Hi-Z
D4 to D7
Hi-Z
start condition
slave address
I / O setting
stop condition
Data output
Data output
Write mode
The terminal assigned as an output provides the data written in the output data latch.
After power-on, all terminals are reset to the input-state. Then an initial data low of the output latch are
output after the I/O setting has been done. Finally the assigned output are provided after the 8-bit data
transmission.
The terminal assigned as an input keeps the input condition (high-impedance) regardless of 8-bit data
setting.
SCL
SDA
0
1
1
1 A2 A1 A0 1
A
D
4
7D
4
6D
4
5D
4
4D
4
3D
4
2D
4
1 D
4
0 A
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
D
3
7D
3
6D
3
5D
3
4 D
3
3D
3
2D
3
1 D
3
0 A
DATA
DATA
D
1
7D
1
6D
1
5D
1
4 D
1
3D
1
2D
1
1D
1
0 A
DATA
D4 to D7
output
Hi-Z
D0 to D3
D
1
X
D
4
X
D
2
X
D
3
X
D4 to D7
(instance)
start condition
slave address
stop condition
data latch
data latch
data latch
Read mode
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