參數(shù)資料
型號(hào)： M5M4V4405CTP-7
廠商： Mitsubishi Electric Corporation
英文描述： EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
中文描述： 江戶（超頁(yè)模式）4194304位（1048576 - Word的4位）動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁(yè)數(shù)： 7/27頁(yè)
文件大?。?/td> 293K
代理商： M5M4V4405CTP-7
EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
M5M4V4405CJ,TP-6,-7,-6S,-7S
MITSUBISHI LSIs
Note 29: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Parameter
Symbol
Limits
Unit
Min
100
110
Max
Min
100
130
Max
Parameter
Symbol
Limits
Unit
Min
5
10
Max
Min
5
15
Max
Parameter
Symbol
Limits
Unit
Min
25
66
Max
Min
30
79
Max
t
RPS
t
CHS
t
RSR
t
RHR
t
RASS
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle.
t
HPC(min)
is specified in the case of read-only and early write-only in Hyper page Mode.
t
RAS(min)
is specified as two cycles of CAS input are performed.
t
CP(max)
)
is specified as a reference point only.
28:
7
Hyper page Mode Cycle
(Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by
CAS before RAS Refresh Cycle
(Note 29)
17
10
10
22
10
15
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
ns
ns
ns
ns
ns
t
CSR
t
CHR
t
RSR
t
RHP
t
CAS
Self Refresh Cycle
*
(Note 30)
10
-50
10
15
-50
10
M5M4V4405C-6,-6S
M5M4V4405C-7,-7S
ns
ns
ns
ns
33
50
7
7
7
32
47
50
15
30
33
77
10
16
100000
38
60
7
7
7
42
57
60
20
35
38
92
13
100000
16
5
5
t
HPC
t
HPRWC
t
DOH
t
RAS
t
CP
t
CPRH
t
CPWD
t
CHOL
t
OEPE
t
WPE
t
HCWD
t
HAWD
t
HPWD
t
HCOD
t
HAOD
t
HPOD
(Note 27)
(Note 28)
(Note 24)
(Note 26)
Note 25:
26:
27:
Hyper page mode read/write cycle time
Hyper Page Mode read write / read modify write cycle time
Output hold time from CAS low
RAS low pulse width for read or write cycle
CAS high pulse width
RAS hold time after CAS precharge
Delay time, CAS precharge to W low
Hold time to maintain the data Hi-Z until CAS access
OE Pulse Width (Hi-Z control)
W Pulse Width (Hi-Z control)
Delay time, CAS low to W low after read
Delay time, Address to W low after read
Delay time, CAS precharge to W low after read
Delay time, CAS low to OE high after read
Delay time, Address to OE high after read
Delay time, CAS precharge to OE high after read
CAS setup time before RAS low
CAS hold time after RAS low
Read setup time before RAS low
Read hold time after RAS low
CAS low pulse width
CBR self refresh RAS low pulse width
CBR self refresh RAS high precharge time
CBR self refresh CAS hold time
Read setup time before RAS low
Read hold time after RAS low
μs
OE or W)
(Note 25)
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