參數(shù)資料
型號(hào)： M5LV-512/120-20HI
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： Fifth Generation MACH Architecture
中文描述： EE PLD, 20 ns, PQFP160
封裝： HEAT SINK, PLASTIC, QFP-160
文件頁(yè)數(shù)： 23/47頁(yè)
文件大小： 1145K
代理商： M5LV-512/120-20HI
MACH 5 Family
3
Note:
1. C = Commercial grade, I = Industrial grade
2. /1 version recommended for new designs
3. Preliminary specicatons
With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512
macrocells to support full system logic integration. Extensive routing resources ensure pinout
retention as well as high utilization. It is ideal for PAL block device integration and a wide range
of other applications including high-speed computing, low-power applications, communications,
and embedded control. At each macrocell density point, Lattice offers several I/O and package
options to meet a wide range of design needs (Table 3).
Note:
1. The I/O options indicated with a “*” are obsolete, please contact factory for more information.
Table 2. MACH 5 Speed Grades
Device
Speed Grade1
-5
-6
-7
-10
-12
-15
-20
M5-1282
C
C, I
I
M5-128/1
C
C, I
I
M5LV-128
C
C,I
C, I
I
M5-192/1
C
C, I
I
M5-2562
C
C, I
I
M5-256/1
C
C, I
I
M5LV-256
C
C, I
I
M5-320
C
C, I
I
M5LV-320
C
C, I
I
M5-384
C3
C, I3
C, I
I
M5LV-384
C3
C, I3
C, I
I
M5-512
C3
C, I3
C, I
I
M5LV-512
C3
C, I3
C, I
I
Table 3. MACH 5 Package and I/O Options 1
M5-128/1
M5LV-128
M5-192/1
M5-256/1
M5LV-256
M5-320
M5LV-320
M5-384
M5LV-384
M5-512
M5LV-512
Supply Voltage
5
3.3
5
3.3
5
3.3
5
3.3
5
3.3
100-pin TQFP
68
68, 74
68
68*, 74
100-pin PQFP
68
68*
68
144-pin TQFP
104
144-pin PQFP
104
104*
160-pin PQFP
120
120*
120
120*
120
120*
120
208-pin PQFP
160
240-pin PQFP
184*
256-ball BGA
192
192*
352-ball BGA
256
相關(guān)PDF資料
PDF描述
M5LV-128/68-12YC Fifth Generation MACH Architecture
M5LV-128/68-12YI Fifth Generation MACH Architecture
M5LV-128/68-15YI Fifth Generation MACH Architecture
M5LV-128/68-5YC Fifth Generation MACH Architecture
M5LV-384/160-6HC Fifth Generation MACH Architecture
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