參數(shù)資料
型號： M5LV-128/68-15YI
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： Fifth Generation MACH Architecture
中文描述： EE PLD, 15 ns, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 4/47頁
文件大?。?/td> 1145K
代理商： M5LV-128/68-15YI
12
MACH 5 Family
initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset
delay time has elapsed.
SECURITY BIT
A programmable security bit is provided on the MACH 5 devices as a deterrent to unauthorized
copying of the array conguration patterns. Once programmed, this bit defeats readback of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
Programming and verication are also defeated by the security bit. The bit can only be reset by
erasing the entire device.
相關(guān)PDF資料
PDF描述
M5LV-128/68-5YC Fifth Generation MACH Architecture
M5LV-384/160-6HC Fifth Generation MACH Architecture
M5LV-384/160-7HC Fifth Generation MACH Architecture
M5LV-384/184-10HC Fifth Generation MACH Architecture
M5LV-384/184-10HI Fifth Generation MACH Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5LV-256/104-10AC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10AI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10HC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10HI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10VC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM HI DENSITY CPLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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