參數(shù)資料
型號： M58WR064EBZB
廠商： 意法半導(dǎo)體
英文描述： 64 Mbit 4Mb x 16, Multiple Bank, Burst 1.8V Supply Flash Memory
中文描述： 64兆位4Mb的× 16，多銀行，突發(fā)1.8V電源快閃記憶體
文件頁數(shù)： 39/82頁
文件大小： 1100K
代理商： M58WR064EBZB
44/82
Figure 14. Clock input AC Waveform
Table 21. Synchronous Read AC Characteristics
Note: 1. Sampled only, not 100% tested.
2. For other timings please refer to Table 20, Asynchronous Read AC Characteristics.
Symbol
Alt
Parameter
VDDQ = 1.65V-2.2V
VDDQ = 2.2V-3.3V
Unit
70
80
100
70
80
100
Sync
hron
ous
R
ead
T
iming
s
tAVKH
tAVCLKH
Address Valid to Clock High
Min
7
9
10
ns
tELKH
tELCLKH
Chip Enable Low to Clock High
Min
7
9
10
ns
tELTV
Chip Enable Low to Wait Valid
Max
14
18
20
22
ns
tEHEL
Chip Enable Pulse Width
(subsequent synchronous reads)
Min
14
20
ns
tEHTZ
Chip Enable High to Wait Hi-Z
Max
14
20
25
ns
tKHAX
tCLKHAX
Clock High to Address Transition
Min
9
10
ns
tKHQV
tKHTV
tCLKHQV
Clock High to Output Valid
Clock High to WAIT Valid
Max
14
18
20
22
ns
tKHQX
tKHTX
tCLKHQX
Clock High to Output Transition
Clock High to WAIT Transition
Min
44
45
55
ns
tLLKH
tADVLCLK
H
Latch Enable Low to Clock High
Min
7
10
ns
C
loc
k
Spec
ificatio
ns
tKHKH
tCLK
Clock Period (f=33MHz)
Min
--
-
30
ns
Clock Period (f=40MHz)
25
Clock Period (f=54MHz)
18.5
-
ns
tKHKL
tKLKH
Clock High to Clock Low
Clock Low to Clock High
Min
4.5
5
9.5
ns
tf
tr
Clock Fall or Rise Time
Max
3
5
ns
AI06981
tKHKH
tf
tr
tKHKL
tKLKH
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