參數(shù)資料
型號(hào)： M58LV064A150N1T
廠商： 意法半導(dǎo)體
英文描述： 64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories
中文描述： 64兆位4Mb的x16或功能的2Mb X32號(hào)，統(tǒng)一座，突發(fā)3V電源閃存
文件頁(yè)數(shù)： 12/65頁(yè)
文件大?。?/td> 450K
代理商： M58LV064A150N1T
M58LV064A, M58LV064B
12/65
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A1-A22).
The Address Inputs
are used to select the cells to access in the mem-
ory array during Bus Read operations either to
read or to program data to. During Bus Write oper-
ations they control the commands sent to the
Command Interface of the internal state machine.
Chip Enable must be low when selecting the ad-
dresses.
The address inputs are latched on the rising edge
of Chip Enable, Write Enable or Latch Enable,
whichever occurs first in a Write operation. The
address latch is transparent when Latch Enable is
low, V
IL
. The address is internally latched in an
Erase or Program operation.
With a x32 Bus Width, WORD = V
IH
, Address In-
put A1 is ignored; the Least Significant Word is
output on DQ0-DQ15 and the Most Significant
Word is output on DQ16-DQ31. With a x16 Bus
Width, WORD = V
IL
, the Least Significant Word is
output on DQ0-DQ15 when A1 is low, V
IL,
and the
Most Significant Word is output on DQ0-DQ15
when A1 is high, V
IH
.
Data Inputs/Outputs (DQ0-DQ31).
The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation, or are used
to input the data during a program operation. Dur-
ing Bus Write operations they represent the com-
mands sent to the Command Interface of the
internal state machine. When used to input data or
Write commands they are latched on the rising
edge of Write Enable or Chip Enable, whichever
occurs first.
When Chip Enable and Output Enable are both
low, V
IL
, the data bus outputs data from the mem-
ory array, the Electronic Signature, the Block Pro-
tection status, the CFI Information or the contents
of the Status Register. The data bus is high imped-
ance when the chip is deselected, Output Enable
is High, V
IH,
or the Reset/Power-Down signal is
Low, V
IL
. When the Program/Erase Controller is
active the Ready/Busy status is given on DQ7
while DQ0-DQ6 and DQ8-DQ31 are high imped-
ance.
With a x16 Bus Width, WORD = V
IL
, DQ16-DQ31
are not used and are high impedance.
Chip Enable (E).
The Chip Enable, E, input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. Chip Enable, E, at
V
IH
deselects the memory and reduces the power
consumption to the Standby level, I
DD1
.
Output Enable (G).
The Output Enable, G, gates
the outputs through the data output buffers during
a read operation. When Output Enable, G, is at V
IH
the outputs are high impedance. Output Enable,
G, can be used to inhibit the data output during a
burst read operation.
Write Enable (W).
The Write Enable input, W,
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data can be latched on the rising edge of Write En-
able (also see Latch Enable, L).
Reset/Power-Down (RP).
The
Down pin can be used to apply a Hardware Reset
to the memory or to temporarily unprotect all
blocks that have been protected.
A Hardware Reset is achieved by holding Reset/
Power-Down Low, V
IL
, for at least t
PLPH
. When
Reset/Power-Down is Low, V
IL
, the Status Regis-
ter information is cleared and the power consump-
tion is reduced to deep power-down level. The
device is deselected and outputs are high imped-
ance. If Reset/Power-Down goes low, V
IL
,during a
Block Erase, a Write to Buffer and Program or a
Block Protect/Unprotect the operation is aborted
and the data may be corrupted. In this case the
Ready/Busy pin stays low, V
IL
, for a maximum tim-
ing of t
PLPH
+ t
PHRH,
until the completion of the Re-
set/Power-Down pulse.
After Reset/Power-Down goes High, V
IH
, the
memory will be ready for Bus Read and Bus Write
operations after t
PHEL
or t
RHEL
, whichever occurs
last. Note that Ready/Busy does not fall during a
reset, see Ready/Busy Output section.
During power-up Reset/Power-Down must be held
Low, V
IL.
Furthermore it must stay low for t
VDHPH
after the Supply Voltage inputs become stable.
The device will then be configured in Asynchro-
nous Random Read mode.
See Table 23 and Figure 21, Reset, Power-Down
and Power-up Characteristics, for more details.
Holding RP at V
HH
will temporarily unprotect the
protected blocks in the memory. Program and
Erase operations on all blocks will be possible.
In an application, it is recommended to associate
Reset/Power-Down pin, RP, with the reset signal
of the microprocessor. Otherwise, if a reset opera-
tion occurs while the memory is performing an
Erase or Program operation, the memory may out-
put the Status Register information instead of be-
ing initialized to the default Asynchronous
Random Read.
Latch Enable (L).
The Bus Interface can be con-
figured to latch the Address Inputs on the rising
edge of Latch Enable, L. In synchronous bus oper-
ations the address is latched on the active edge of
the Clock when Latch Enable is Low, V
IL
. Once
latched, the addresses may change without affect-
ing the address used by the memory. When Latch
Enable is Low, V
IL
, the latch is transparent.
Reset/Power-
相關(guān)PDF資料
PDF描述
M58LV064A150N6T 64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LV064A150ZA6T 64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW032C 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory
M58LW032C110N1 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory
M58LW032C110N1E 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58LV064A150N6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LV064A150ZA1 功能描述:閃存 4Mx16 or 2Mx32 150ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
M58LV064A150ZA1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LV064A150ZA6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LV064B 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit 4Mb x16 or 2Mb x32, Uniform Block, Burst 3V Supply Flash Memories
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*