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參數(shù)資料
| 型號： | M5-320/192-12AC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Fifth Generation MACH Architecture |
| 中文描述： | EE PLD, 12 ns, PBGA256 |
| 封裝： | BGA-256 |
| 文件頁數(shù)： | 4/47頁 |
| 文件大?。?/td> | 1145K |
| 代理商： | M5-320/192-12AC |
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12
MACH 5 Family
initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset
delay time has elapsed.
SECURITY BIT
A programmable security bit is provided on the MACH 5 devices as a deterrent to unauthorized
copying of the array conguration patterns. Once programmed, this bit defeats readback of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
Programming and verication are also defeated by the security bit. The bit can only be reset by
erasing the entire device.
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| M5-320/192-12AI | Fifth Generation MACH Architecture |
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| M5-384/120-12HI | Fifth Generation MACH Architecture |
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