參數(shù)資料
型號： M5-256/68-7VC
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： Fifth Generation MACH Architecture
中文描述： EE PLD, 7.5 ns, PQFP100
封裝： TQFP-100
文件頁數(shù)： 6/42頁
文件大小： 938K
代理商： M5-256/68-7VC
14
MACH 5 Family
BLOCK DIAGRAM — M5(LV)-128/XXX
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Block A/Macrocells 0-15
Block D/Macrocells 0-15
Block B/Macrocells 0-15
Block C/Macrocells 0-15
Block Interconnect
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
64 x 73
AND Logic Array
and Logic Allocator
Control
Generator
64 PT
2 PT OE
I/O Cells
16
32
7 PT
7
2
32
16
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Macrocells
Control
Generator
64 PT
2 PT OE
16
32
7 PT
7
2
32
16
I/O Cells
64 x 73
AND Logic Array
and Logic Allocator
Block A/Macrocells 0-15
Block D/Macrocells 0-15
Block B/Macrocells 0-15
Block C/Macrocells 0-15
Block Interconnect
S E G M E N T I N T E R C O N N E C T
CLK0
CLK1
CLK2
CLK3
4
SEGMENT 0
SEGMENT 1
I0, 1
I2, 3
2
20446G-007
相關(guān)PDF資料
PDF描述
M5-256/68-7VI Fifth Generation MACH Architecture
M5-320/160-12YC Fifth Generation MACH Architecture
M5-320/160-12YI Fifth Generation MACH Architecture
M5-320/160-15YC Fifth Generation MACH Architecture
M5-320/160-15YI Fifth Generation MACH Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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M5265P 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:LOW SATURATION OUTPUT TYPE CURRENT DRIVER
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