參數(shù)資料
型號(hào)： M4LV-96/48-7VC
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： High Performance E 2 CMOS In-System Programmable Logic
中文描述： EE PLD, 7.5 ns, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 43/46頁(yè)
文件大?。?/td> 754K
代理商： M4LV-96/48-7VC
6MACH 4 Family
Table 4. Architectural Summary of MACH 4 devices
The Macrocell-I/O cell ratio is dened as the number of macrocells versus the number of I/O
cells internally in a PAL block (Table 4).
The central switch matrix takes all dedicated inputs and signals from the input switch matrices
and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block
still must go through the central switch matrix. This mechanism ensures that PAL blocks in MACH
4 devices communicate with each other with consistent, predictable delays.
The central switch matrix makes a MACH 4 device more advanced than simply several PAL
devices on a single chip. It allows the designer to think of the device not as a collection of
blocks, but as a single programmable device; the software partitions the design into PAL blocks
through the central switch matrix so that the designer does not have to be concerned with the
internal architecture of the device.
Each PAL block consists of:
◆ Product-term array
◆ Logic allocator
◆ Macrocells
◆ Output switch matrix
◆ I/O cells
◆ Input switch matrix
◆ Clock generator
MACH 4 Devices
M4-64/32, M4LV-64/32
M4-96/48, M4LV-96/48
M4-128/64, M4LV-128/64
M4-128N/64, M4LV-128N/64
M4-192/96, M4LV-192/96
M4-256/128, M4LV-256/128
M4-32/32
M4LV-32/32
Macrocell-I/O Cell
Ratio
2:1
1:1
Input Switch Matrix
Yes
Input Registers
Yes
No
Central Switch Matrix
Yes
Output Switch Matrix
Yes
相關(guān)PDF資料
PDF描述
M4LV-256/128-10YI High Performance E 2 CMOS In-System Programmable Logic
M4LV-64/32-18VI High Performance E 2 CMOS In-System Programmable Logic
M4-256/128-12AC High Performance E 2 CMOS In-System Programmable Logic
M4-256/128-12AI High Performance E 2 CMOS In-System Programmable Logic
M4-256/128-15AC High Performance E 2 CMOS In-System Programmable Logic
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