參數(shù)資料
型號(hào): M4LV-96/48-12VC
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: High Performance E 2 CMOS In-System Programmable Logic
中文描述: EE PLD, 12 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 2/46頁
文件大小: 754K
代理商: M4LV-96/48-12VC
10
MACH 4 Family
Macrocell
The macrocell consists of a storage element, routing resources, a clock multiplexer, and
initialization control. The macrocell has two fundamental modes: synchronous and
asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the
macrocell.
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous
mode will generally be used, since it provides more product terms in the allocator.
SWAP
D/T/L
Q
AP
AR
Power-Up
Reset
PAL-Block
Initialization
Product Terms
From Logic Allocator
Block CLK0
Block CLK1
Block CLK2
Block CLK3
To Output and Input
Switch Matrices
Common PAL-block resource
Individual macrocell resources
From
PAL-Clock
Generator
D/T/L
Q
AP
AR
Power-Up
Reset
Individual
Initialization
Product Term
From Logic
Allocator
Block CLK0
Block CLK1
To Output and Input
Switch Matrices
Individual Clock
Product Term
From PAL-Block
Clock Generator
17466G-010
Figure 5. Macrocell
17466G-009
a. Synchronous mode
b. Asynchronous mode
相關(guān)PDF資料
PDF描述
M4LV-96/48-12VI High Performance E 2 CMOS In-System Programmable Logic
M4LV-96/48-15VC High Performance E 2 CMOS In-System Programmable Logic
M4LV-96/48-18VI High Performance E 2 CMOS In-System Programmable Logic
M4LV-96/48-7VC High Performance E 2 CMOS In-System Programmable Logic
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