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參數(shù)資料
| 型號： | M48T201Y-70MH1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復及定時提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封裝： | SNAPHAT, PLASTIC, SOIC-44 |
| 文件頁數(shù)： | 9/37頁 |
| 文件大?。?/td> | 311K |
| 代理商： | M48T201Y-70MH1 |
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M48T201Y, M48T201V
Clock operation
3
Clock operation
3.1
TIMEKEEPER registers
The M48T201Y/V offers 16 internal registers which contain TIMEKEEPER, alarm,
watchdog, flag, and control data (see Table5 on page18). These registers are memory
locations which contain external (user accessible) and internal copies of the data (usually
referred to as BiPORT TIMEKEEPER cells). The external copies are independent of
internal functions except that they are updated periodically by the simultaneous transfer of
the incremented internal copy. TIMEKEEPER and alarm registers store data in BCD.
control, watchdog and flags (bits D0 to D3) registers store data in binary format.
3.2
Reading the clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent
reading data in transition. The BiPORT TIMEKEEPER cells in the RAM array are only data
registers and not the actual clock counters, so updating the registers can be halted without
disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register (7FFF8h).
As long as a '1' remains in that position, updating is halted. After a halt is issued, the
registers reflect the count; that is, the day, date, and time that were current at the moment
the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating occurs approximately 1 second after the READ bit is reset to a
'0.'
3.3
Setting the clock
Bit D7 of the control register (7FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like
the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them
with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 18).
Resetting the WRITE bit to a '0' then transfers the values of all time registers (7FFFFh-
7FFF9h, 7FFF1h) to the actual TIMEKEEPER counters and allows normal operation to
resume. After the WRITE bit is reset, the next clock update will occur approximately one
second later.
Note:
Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset
to '0.'
3.4
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is located at bit D7 within the seconds register (7FFF9h). Setting it to
a '1' stops the oscillator. When reset to a '0,' the M48T201Y/V oscillator starts within one
second.
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| M48T201Y-70MH1E | 1 TIMER(S), REAL TIME CLOCK, PDSO44 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M48T201Y-70MH1E | 功能描述:監(jiān)控電路 SRAM TK Controller RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| M48T201Y-70MH1F | 功能描述:監(jiān)控電路 SRAM TK Controller RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| M48T201Y-70MH1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V TIMEKEEPER㈢ supervisor |
| M48T201Y-80MH1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V TIMEKEEPER? supervisor |
| M48T201Y-80MH1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V TIMEKEEPER? supervisor |
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