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參數(shù)資料
| 型號： | M48T12-200PC1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 16 Kbit 2Kb x8 TIMEKEEPER[ SRAM |
| 中文描述： | 16千位2KB的x8計時器[靜態(tài)存儲器 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 94K |
| 代理商： | M48T12-200PC1 |
Symbol
Parameter
Min
Max
Unit
tPD
E or W at VIH before Power Down
0
s
tF
(1)
VPFD (max) to VPFD (min) VCC Fall Time
300
s
tFB
(2)
VPFD (min) to VSO VCC Fall Time
10
s
tR
VPFD(min) to VPFD (max) VCC Rise Time
0
s
tRB
VSO to VPFD (min) VCC Rise Time
1
s
tREC
E or W at VIH after Power Up
2
ms
Notes:1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 50
s after
VCC passes VPFD (min).
2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data.
Table 8. Power Down/Up Mode AC Characteristics
(TA = 0 to 70
°C)
AI00606
VCC
INPUTS
(PER CONTROL INPUT)
OUTPUTS
DON’T CARE
HIGH-Z
tF
tFB
tR
tREC
tPD
tRB
tDR
VALID
NOTE
(PER CONTROL INPUT)
RECOGNIZED
VPFD (max)
VPFD (min)
VSO
Figure 5. Power Down/Up Mode AC Waveforms
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD(min). Some systems
may perform inadvertent write cycles after VCC rises above VPFD(min) but before normal system operations begin. Even though a power on
reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
5/15
M48T02, M48T12
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| M48T12-200PC1 | 制造商:STMicroelectronics 功能描述:SRAM TIMEKEEPER 16K 48T12 DIP24 |
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