參數(shù)資料
型號: M391T2953CZ3-CCC
元件分類: DRAM
英文描述: 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁數(shù): 6/24頁
文件大?。?/td> 780K
代理商: M391T2953CZ3-CCC
Rev. 1.5 October 2006
UDIMM
DDR2 SDRAM
14 of 24
10.2 Operating Temperature Condition
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM.
2. At 85 - 95
°C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
10.3 Input DC Logic Level
10.4 Input AC Logic Level
10.5 AC Input Test Conditions
Note :
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative
transitions.
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°C
1, 2
Symbol
Parameter
Min.
Max.
Units
Notes
VIH (DC)
DC input logic high
VREF + 0.125
VDDQ + 0.3
V
VIL (DC)
DC input logic low
- 0.3
VREF - 0.125
V
Symbol
Parameter
DDR2-400, DDR2-533
DDR2-667, DDR2-800
Units
Notes
Min.
Max.
Min.
Max.
VIH (AC)
AC input logic high
VREF + 0.250
-
VREF + 0.200
V
VIL (AC)
AC input logic low
-
VREF - 0.250
VREF - 0.200
V
Symbol
Condition
Value
Units
Notes
VREF
Input reference voltage
0.5 * VDDQ
V1
VSWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
VDDQ
VIH(AC) min
VIH(DC) min
VREF
VIL(DC) max
VIL(AC) max
VSS
< AC Input Test Signal Waveform >
VSWING(MAX)
delta TR
delta TF
VREF - VIL(AC) max
delta TF
Falling Slew =
Rising Slew =
VIH(AC) min - VREF
delta TR
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