參數(shù)資料
型號： M38C37ECMFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 22/65頁
文件大?。?/td> 808K
代理商： M38C37ECMFP
26
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
A-D CONVERTER
The 38C3 group has a 10-bit A-D converter. The A-D converter per-
forms successive approximation conversion.
[A-D Conversion Register (AD)] 003316, 003416
One of these registers is a high-order register, and the other is a low-
order register. The high-order 8 bits of a conversion result is stored in
the A-D conversion register (high-order) (address 003416), and the
low-order 2 bits of the same result are stored in bit 7 and bit 6 of the
A-D conversion register (low-order) (address 003316).
During A-D conversion, do not read these registers.
[A-D Control Register (ADCON)] 003216
This register controls A-D converter. Bits 2 to 0 are analog input pin
selection bits. Bit 4 is an AD conversion completion bit and “0” during
A-D conversion. This bit is set to “1” upon completion of A-D conver-
sion.
A-D conversion is started by setting “0” in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS
and VREF, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P67/AN7–P60/
AN0 and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the con-
trol circuit sets the AD conversion completion bit and the AD conver-
sion interrupt request bit to “1.”
Fig. 26 Block diagram of A-D converter
Note that the comparator is constructed linked to a capacitor, so set
f(XIN) to at least 500 kHz during A-D conversion. Use a CPU system
clock dividing the main clock XIN as the internal system clock.
Fig. 25 Structure of A-D control register
AD conversion result stored bits
A-D conversion register (high-order)
(ADH: address 003416)
b7
b0
Analog input pin selection bits
000: P60/AN0
001: P61/AN1
010: P62/AN2
011: P63/AN3
100: P64/AN4
101: P65/AN5
110: P66/AN6
111: P67/AN7
A-D control register
(ADCON: address 003216)
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
b7
b0
Not used (returns “0” when read)
AD conversion result stored bits
A-D conversion register (low-order)
(ADL: address 003316)
b7
b0
Not used (returns “0” when read)
Data bus
AVSS
A-D interrupt request
b7
b0
3
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
A-D control register
Channel
selector
Comparator
A-D control circuit
A-D conversion register (H)
A-D conversion register (L)
(Address 0034 16)
(Address 0033 16)
Resistor ladder
VREF
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