參數(shù)資料
型號(hào)： M38859M8-XXXHP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 45/103頁(yè)
文件大?。?/td> 1580K
代理商： M38859M8-XXXHP
44
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Example of Master Transmission
An example of master transmission in the standard clock mode, at
the S
CL
frequency of 100 kHz and in the ACK return mode is
shown below.
(1) Set a slave address in the high-order 7 bits of the I
2
C address
register (S0D) and
“
0
”
into the RWB bit.
(2) Set the ACK return mode and S
CL
= 100 kHz by setting
“
85
16
”
in the I
2
C clock control register (S2).
(3) Set
“
00
16
”
in the I
2
C status register (S1) so that transmission/
reception mode can become initializing condition.
(4) Set a communication enable status by setting
“
08
16
”
in the I
2
C
control register (S1D).
(5) Confirm the bus free condition by the BB flag of the I
2
C status
register (S1).
(6) Set the address data of the destination of transmission in the
high-order 7 bits of the I
2
C data shift register (S0) and set
“
0
”
in the least significant bit.
(7) Set
“
F0
16
”
in the I
2
C status register (S1) to generate a START
condition. At this time, an S
CL
for 1 byte and an ACK clock au-
tomatically occur.
(8) Set transmit data in the I
2
C data shift register (S0). At this time,
an S
CL
and an ACK clock automatically occur.
(9) When transmitting control data of more than 1 byte, repeat step
(8).
(10) Set
“
D0
16
”
in the I
2
C status register (S1) to generate a STOP
condition if ACK is not returned from slave reception side or
transmission ends.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the S
CL
frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
(1) Set a slave address in the high-order 7 bits of the I
2
C address
register (S0D) and
“
0
”
in the RWB bit.
(2) Set the no ACK clock mode and S
CL
= 400 kHz by setting
“
25
16
”
in the I
2
C clock control register (S2).
(3) Set
“
00
16
”
in the I
2
C status register (S1) so that transmission/
reception mode can become initializing condition.
(4) Set a communication enable status by setting
“
08
16
”
in the I
2
C
control register (S1D).
(5) When a START condition is received, an address comparison
is performed.
(6)
When all transmitted addresses are
“
0
”
(general call):
AD0 of the I
2
C status register (S1) is set to
“
1
”
and an interrupt
request signal occurs.
When the transmitted address matches with the address set
in (1):
ASS of the I
2
C status register (S1) is set to
“
1
”
and an interrupt
request signal occurs.
In the cases other than the above AD0 and AAS of the I
2
C
status register (S1) are set to
“
0
”
and no interrupt request sig-
nal occurs.
(7) Set dummy data in the I
2
C data shift register (S0).
(8) When receiving control data of more than 1 byte, repeat step (7).
(9) When a STOP condition is detected, the communication ends.
I
Precautions when using multi-master I
2
C-
BUS interface
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
I
2
C-BUS interface are described below.
I
2
C data shift register (S0: address 0012
16
)
When executing the read-modify-write instruction for this regis-
ter during transfer, data may become a value not intended.
I
2
C address register (S0D: address 0013
16
)
When the read-modify-write instruction is executed for this regis-
ter at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RWB) at the above timing.
I
2
C status register (S1: address 0014
16
)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by H/W.
I
2
C control register (S1D: address 0015
16
)
When the read-modify-write instruction is executed for this regis-
ter at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
I
2
C clock control register (S2: address 0016
16
)
The read-modify-write instruction can be executed for this register.
I
2
C START/STOP condition control register (S2D: address
0017
16
)
The read-modify-write instruction can be executed for this register.
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