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| 型號： | M38855FA-HP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 38/103頁 |
| 文件大?。?/td> | 1580K |
| 代理商： | M38855FA-HP |
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37
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Table 11 Set values of I
2
C clock control register and S
CL
frequency
Setting value of
CCR4
–
CCR0
Standard clock
CCR4
CCR3
CCR2
CCR1
CCR0
Fig. 33 Structure of I
2
C clock control register
S
CL
frequency
(at
φ
= 4 MHz, unit : kHz)
(Note 1)
mode
Setting disabled
Setting disabled
Setting disabled
–
(Note 2)
–
(Note 2)
100
83.3
High-speed clock
mode
Setting disabled
Setting disabled
Setting disabled
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
Notes 1:
Duty of S
CL
clock output is 50 %. The duty becomes 35 to 45 %
only when the high-speed clock mode is selected and CCR value
= 5 (400 kHz, at
φ
= 4 MHz).
“
H
”
duration of the clock fluctuates
from
–
4 to +2 cycles of
φ
in the standard clock mode, and fluctu-
ates from
–
2 to +2 cycles of
φ
in the high-speed clock mode. In
the case of negative fluctuation, the frequency does not increase
because
“
L
”
duration is extended instead of
“
H
”
duration reduc-
tion.
These are value when S
CL
clock synchronization by the synchro-
nous function is not performed. CCR value is the decimal
notation value of the S
CL
frequency control bits CCR4 to CCR0.
2:
Each value of S
CL
frequency exceeds the limit at
φ
= 4 MHz or
more. When using these setting value, use
φ
of 4 MHz or less.
3:
The data formula of S
CL
frequency is described below:
φ
/(8
CCR value) Standard clock mode
φ
/(4
CCR value) High-speed clock mode (CCR value
≠
5)
φ
/(2
CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of
φ
frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz
(max.) in the high-speed clock mode to the S
CL
frequency by set-
ting the S
CL
frequency control bits CCR4 to CCR0.
…
…
…
…
…
1000/CCR value
(Note 3)
34.5
33.3
32.3
500/CCR value
(Note 3)
17.2
16.6
16.1
333
250
400
(Note 3)
166
[I
2
C Clock Control Register (S2)] 0016
16
The I
2
C clock control register (S2) is used to set ACK control, S
CL
mode and S
CL
frequency.
Bits 0 to 4: S
CL
frequency control bits (CCR0–CCR4)
These bits control the S
CL
frequency. Refer to Table 11.
Bit 5: S
CL
mode specification bit (FAST MODE)
This bit specifies the S
CL
mode. When this bit is set to
“
0
”
, the
standard clock mode is selected. When the bit is set to
“
1
”
, the
high-speed clock mode is selected.
When connecting the bus of the high-speed mode I
2
C bus stan-
dard (maximum 400 kbits/s), use 8 MHz or more oscillation
frequency f(X
IN
) and high-speed mode (2 division main clock).
Bit 6: ACK bit (ACK BIT)
This bit sets the S
DA
status when an ACK clock
is generated.
When this bit is set to
“
0
”
, the ACK return mode is selected and
S
DA
goes to
“
L
”
at the occurrence of an ACK clock. When the bit is
set to
“
1
”
, the ACK non-return mode is selected. The S
DA
is held in
the
“
H
”
status at the occurrence of an ACK clock.
However, when the slave address matches with the address data
in the reception of address data at ACK BIT =
“
0
”
, the S
DA
is au-
tomatically made
“
L
”
(ACK is returned). If there is a unmatch
between the slave address and the address data, the S
DA
is auto-
matically made
“
H
”
(ACK is not returned).
ACK clock: Clock for acknowledgment
Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which is an ac-
knowledgment response of data transfer. When this bit is set to
“
0
”
, the no ACK clock mode is selected. In this case, no ACK clock
occurs after data transmission. When the bit is set to
“
1
”
, the ACK
clock mode is selected and the master generates an ACK clock
each completion of each 1-byte data transfer. The device for
transmitting address data and control data releases the S
DA
at the
occurrence of an ACK clock (makes S
DA
“
H
”
) and receives the
ACK bit generated by the data receiving device.
Note:
Do not write data into the I
2
C clock control register during transfer. If
data is written during transfer, the I
2
C clock generator is reset, so
that data cannot be transferred normally.
ACK
BIT
FAST
I
2
C clock control register
(S2 : address 0016
16
)
b7
b0
S
CL
frequency control
bits
Refer to Table 11.
S
CL
mode specification bit
0 : Standard clock mode
1 : High-speed clock
mode
ACK bit
0 : ACK is returned.
1 : ACK is not
returned.
ACK clock bit
0 : No ACK clock
1 : ACK clock
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