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參數(shù)資料
| 型號： | M38855F2-HP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 28/103頁 |
| 文件大?。?/td> | 1580K |
| 代理商： | M38855F2-HP |
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27
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Basic Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (WDTCON) after resetting, the watchdog timer is in the stop
state. The watchdog timer starts to count down by writing an op-
tional value into the watchdog timer control register (WDTCON) and
an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (WDTCON) may be started be-
fore an underflow. When the watchdog timer control register
(WDTCON) is read, the values of the high-order 6 bits of the
watchdog timer H, STP instruction disable bit, and watchdog timer
H count source selection bit are read.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register
(WDTCON), each watchdog timer H and L is set to “FF
16
”.
Fig. 22 Structure of Watchdog timer control register
G
Watchdog timer H count source selection bit operation
Bit 7 of WDTCON permits selecting a watchdog timer H count
source. When this bit is set to “0”, the count source becomes the
underflow signal of watchdog timer L. The detection time is set to
131.072 ms at f(X
IN
)=8 MHz and 32.768 s at f(X
CIN
)=32 kHz .
When this bit is set to “1”, the count source becomes the signal
divided by 16 for f(X
IN
) (or f(X
CIN
) in low speed mode). The detec-
tion time in this case is set to 512
μ
s at f(X
IN
)=8 MHz and 128 ms
at f(X
CIN
)=32 kHz . This bit is cleared to “0” after resetting.
G
STP instruction disable bit
Bit 6 of WDTCON permits disabling the STP instruction when the
watchdog timer is in operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
When this bit is “1”, the STP instruction execution cause an inter-
nal reset. When this bit is set to “1”, it cannot be rewritten to “0” by
program. This bit is cleared to “0” after resetting.
Fig. 21 Block diagram of Watchdog timer
X
IN
Data bus
X
CIN
“
10
”
“
00
”
“
01
”
Main clock division
ratio selection bits
(Note)
“
0
”
“
1
”
1/16
Watchdog timer H count
source selection bit
Reset
circuit
STP instruction disable bit
STP instruction
Watchdog timer H (8)
“
FF
16
”
is set when
watchdog timer
control register is
written to.
Internal reset
RESET
Watchdog timer L (8)
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
“
FF
16
”
is set when
watchdog timer
control register is
written to.
b0
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(X
IN
)/16 or f(X
CIN
)/16
Watchdog timer H (for read-out of high-order 6 bit)
Watchdog timer control register
(WDTCON : address 001E
16
)
b
7
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相關代理商/技術參數(shù) |
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|---|---|
| M38855F3-HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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