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參數(shù)資料
| 型號(hào)： | M38853ME-XXXHP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 74/103頁 |
| 文件大?。?/td> | 1580K |
| 代理商： | M38853ME-XXXHP |
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3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
73
Bus Operation Modes
Read
The Read mode is entered by pulling the OE pin low when the CE
pin is low and the WE and RP pins are high. There are two read
modes: array, and status register, which are selected by software
command input. In read mode, the data corresponding to each soft-
ware command entered is output from the data I/O pins D
0
–
D
7
. The
read array mode is automatically selected when the device is pow-
ered on or after it exits deep power down mode.
Output Disable
The output disable mode is entered by pulling the CE pin low and the
WE, OE, and RP pins high. Also, the data I/O pins are placed in the
high-impedance state.
Standby
The standby mode is entered by driving the CE pin high when the RP
pin is high. Also, the data I/O pins are placed in the high-impedance
state. However, if the CE pin is set high during erase or program
operation, the internal control circuit does not halt immediately and
normal power consumption is required until the operation under way
is completed.
Write
The write mode is entered by pulling the WE pin low when the CE pin
is low and the OE and RP pins are high. In this mode, the device
accepts the software commands or write data entered from the data
I/O pins. A program, erase, or some other operation is initiated de-
pending on the content of the software command entered here. The
input data such as address and software command is latched at the
rising edge of WE or CE whichever occurs earlier.
Deep Power Down
The deep power down is entered by pulling the RP pin low. Also, the
data I/O pins are placed in the high-impedance state. When the de-
vice is freed from deep power down mode, the read array mode is
“
80
16
.
”
If the
RP pin is pulled low during erase or program operation, the opera-
tion under way is canceled and the data in the relevant block be-
comes invalid.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Fig-
ure 72 can be rewritten. The BSEL pin is used to choose between these
two areas. The user ROM area is selected by pulling the BSEL input
low; the boot ROM area is selected by driving the BSEL input high. Both
areas of flash memory can be operated on in the same way.
Program and block erase operations can be performed in the user ROM
area. The user ROM area and its blocks are shown in Figure 72.
The user ROM area is 60 Kbytes in size. In parallel I/O mode, it is
located at addresses 1000
16
through FFFF
16
. The boot ROM area is
4 Kbytes in size. In parallel I/O mode, it is located at addresses
F000
16
through FFFF
16
. Make sure program and block erase opera-
tions are always performed within this address range. (Access to any
location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block.
Functional Outline (Parallel I/O Mode)
In parallel I/O mode, bus operation modes
—
Read, Output Disable,
Standby, Write, and Deep Power Down
—
are selected by the status
of the CE, OE, WE, and RP input pins.
The contents of erase, program, and other operations are selected
by writing a software command. The data, status register, etc. in
memory can only be read out by a read after software command
input.
Program and erase operations are controlled using software com-
mands.
The following explains about bus operation modes, software com-
mands, and status register.
D
0
to D
7
Data output
Status register data output
Hi-z
Hi-z
Command/data input
Command input
Command input
Hi-z
RP
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IH
V
IL
WE
V
IH
V
IH
V
IH
X
V
IL
V
IL
V
IL
X
OE
V
IL
V
IL
V
IH
X
V
IH
V
IH
V
IH
X
CE
V
IL
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
X
Pin name
Mode
Array
Status register
Output disabled
Stand by
Program
Erase
Other
Write
Deep power down
Note :
X can be V
IL
or V
IH
.
Read
Table 19 Relationship between control signals and bus operation modes
Parallel I/O Mode
The parallel I/O mode is entered by making connections shown in
Figures 73 and then turning the Vcc power supply on.
Address
The user ROM is divided into two blocks as shown in Figure 72. The
block address referred to in this data sheet is the maximum address
value of each block.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M38853MF-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38854F1-HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38854F2-HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38854F3-HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38854F4-HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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