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參數(shù)資料
| 型號： | M38507F8SP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 78/103頁 |
| 文件大?。?/td> | 1275K |
| 代理商： | M38507F8SP |
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Rev.3.01
2003.06.20
page 74 of 98
3850 Group (Spec.H/A)
qStatus Register 1 (SRD1)
The status register 1 indicates the status of serial communica-
tions, results from ID checks and results from check sum
comparisons. It can be read after the status register (SRD) by writ-
ing the read status register command (7016). Also, status register
1 is cleared by writing the clear status register command (5016).
Table 17 lists the definition of each status register 1 bit. This regis-
ter becomes “0016” when power is turned on and the flag status is
maintained even after the reset.
Table 17 Definition of each bit of status register 1 (SRD1)
00
Not verified
01
Verification mismatch
10
Reserved
11
Verified
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
SR9 (bit1)
SR8 (bit0)
Boot update completed bit
Reserved
Checksum match bit
ID check completed bits
Data reception time out
Reserved
“1”
Update completed
-
Match
Time out
-
“0”
Not Update
-
Mismatch
Normal operation
-
Definition
SRD1 bits
Status name
Boot update completed bit (SR15)
This flag indicates whether the control program was downloaded
to the RAM or not, using the download function.
Check sum consistency bit (SR12)
This flag indicates whether the check sum matches or not when a
program, is downloaded for execution using the download func-
tion.
ID check completed bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands
cannot be accepted without an ID code check.
Data reception time out (SR9)
This flag indicates when a time out error is generated during data
reception. If this flag is attached during data reception, the re-
ceived data is discarded and the MCU returns to the command
wait state.
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