參數(shù)資料
型號(hào)： M38504M6A-XXXFP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42
封裝： 8.40 X 17.50 MM, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁(yè)數(shù)： 86/90頁(yè)
文件大小： 899K
代理商： M38504M6A-XXXFP
3850 Group (Spec.A)
Rev.2.10
2005.11.14
page 85 of 86
REJ03B0093-0210
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Notes on A/D converter
1. Analog input pin
Make the signal source impedance for analog input low, or equip an
analog input pin with an external capacitor of 0.01
F to 1 F. Further,
be sure to verify the operation of application products on the user side.
<Reason>
An analog input pin includes the capacitor for analog voltage compari-
son. Accordingly, when signals from signal source with high impedance
are input to an analog input pin, charge and discharge noise gener-
ates. This may cause the A/D conversion precision to be worse.
2. A/D converter power source pin
The AVSS pin is A/D converter power source pin. Regardless of
using the A/D conversion function or not, connect it as following :
AVSS : Connect to the VSS line
<Reason>
If the AVSS pin is opened, the microcomputer may have a failure
because of noise or others.
3. Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of
the capacity will be lost if the clock frequency is too low. Thus,
make sure the following during an A/D conversion.
f(XIN) is 500 kHz or more in middle-/high-speed mode.
Do not execute the STP instruction.
When the A/D converter is operated at low-speed mode, f(XIN)
do not have the lower limit of frequency, because of the A/D con-
verter has a built-in self-oscillation circuit.
Notes on watchdog timer
Make sure that the watchdog timer does not underflow while
waiting Stop release, because the watchdog timer keeps count-
ing during that term.
When the STP instruction disable bit has been set to “1”, it is im-
possible to switch it to “0” by a program.
____________
Notes on RESET pin
1. Connecting capacitor
____________
In case where the RESET signal rise time is long, connect a ce-
____________
ramic capacitor or others across the RESET pin and the VSS pin.
Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
Make the length of the wiring which is connected to a capacitor
as short as possible.
Be sure to verify the operation of application products on the
user side.
<Reason>
If the several nanosecond or several ten nanosecond impulse noise
____________
enters the RESET pin, it may cause a microcomputer failure.
2. Reset release after power on
When releasing the reset after power on, such as power-on reset,
release reset after XIN passes more than 20 cycles in the state
where the power supply voltage is 2.7 V or more and the XIN oscil-
lation is stable.
<Reason>
____________
To release reset, the RESET pin must be held at an “L” level for 20
cycles or more of XIN in the state where the power source voltage
is between 2.7 V and 5.5 V, and XIN oscillation is stable.
Notes on using stop mode
1. Register setting
Since values of the prescaler 12 and Timer 1 are automatically re-
loaded when returning from the stop mode, set them again,
respectively. (When the oscillation stabilizing time set after STP in-
struction released bit is “0”)
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
2. Clock restoration
After restoration from the stop mode to the normal mode by an in-
terrupt request, the contents of the CPU mode register previous to
the STP instruction execution are retained. Accordingly, if both main
clock and sub clock were oscillating before execution of the STP in-
struction, the oscillation of both clocks is resumed at restoration.
In the above case, when the main clock side is set as a system
clock, the oscillation stabilizing time for approximately 8,000
cycles of the XIN input is reserved at restoration from the stop
mode. At this time, note that the oscillation on the sub clock side
may not be stabilized even after the lapse of the oscillation stabi-
lizing time of the main clock side.
Notes on wait mode
Clock restoration
If the wait mode is released by a reset when XCIN is set as the
system clock and XIN oscillation is stopped during execution of the
WIT instruction, XCIN oscillation stops, XIN oscillations starts, and
XIN is set as the system clock.
____________
In the above case, the RESET pin should be held at “L” until the
oscillation is stabilized.
Notes on CPU rewrite mode of flash memory
version
1. Operation speed
During CPU rewrite mode, set the internal clock frequency 4MHz
or less by using the main clock division ratio selection bits (bits 6,
7 at address 003B16).
2. Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode .
3. Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
4. Watchdog timer
In case of the watchdog timer has been running already, the inter-
nal reset generated by watchdog timer underflow does not
happen, because of watchdog timer is always clearing during pro-
gram or erase operation.
5. Reset
Reset is always valid. In case of CNVSS = “H” when reset is re-
leased, boot mode is active. So the program starts from the address
contained in addresses FFFC16 and FFFD16 in boot ROM area.
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