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參數(shù)資料
| 型號： | M38503M2A-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42 |
| 封裝： | 8.40 X 17.50 MM, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件頁數(shù)： | 17/59頁 |
| 文件大?。?/td> | 885K |
| 代理商： | M38503M2A-XXXFP |
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Rev.2.13
Apr 17, 2009
Page 24 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
SERIAL INTERFACE
Serial I/O1
Serial I/O1 can be used as either clock synchronous or
asynchronous (UART) serial I/O1. A dedicated timer is also
provided for baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Fig 20. Block diagram of clock synchronous serial I/O1
Fig 21. Operation of clock synchronous serial I/O1 function
Serial I/O1 control register
Receive buffer register
Receive shift register
Clock control circuit
1/4
Baud rate generator
XIN
1/4
Clock control circuit
Falling-edge detector
Transmit buffer register
Transmit shift register
Serial I/O1 status register
F/F
Address 001816
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Shift clock
Serial I/O1 synchronous clock selection bit
Frequency division ratio 1/(n+1)
Address 001C16
BRG count source selection bit
Address 001816
Shift clock
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001916
Address 001A16
Data bus
P26/SCLK1
P24/RXD
P25/TXD
P27/SRDY1
D7
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TXD
Serial input RXD
Write pulse to receive/transmit
buffer register (address 001816)
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended
(TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output
continuously from the TXD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Receive enable signal SRDY1
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