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參數(shù)資料
| 型號： | M38259EFHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 36/70頁 |
| 文件大?。?/td> | 607K |
| 代理商： | M38259EFHP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
36
CLOCK OUTPUT FUNCTION
Input/output ports P4
0
and P4
1
can output clock. The input/output
ports and clock output function are put under double function con-
trolled by the clock output control register (address 002A
16
).
Selection of Input/Output Ports and Clock
Output Function
Bits 0 and 1 of the clock output control register can select between
the input/output ports and the clock output function.
When selecting the clock output function, clocks are output while
the direction register of ports P4
0
and P4
1
are set to output.
At the next cycle of rewriting the clock output control bit, P4
0
is
switched between the port output and the clock output.
In synchronization with the fall of the clock (resulting from dividing
X
IN
by 5) on rewriting the clock output control bit, P4
1
is switched
between the port output and the clock output.
Selection of Output Clock Frequency
Bit 2 (output clock frequency selection bit) of the clock output con-
trol register selects an output clock frequency.
When setting the output clock frequency selection bit to “0”, port
P4
0
becomes the frequency of f(X
IN
) and port P4
1
becomes the
frequency of f(X
IN
)/5.
At this time, the output pulse of port P4
0
depends on the X
IN
input
pulse, while the output pulse of port P4
1
has duty ratio of about
40%.
When setting the output clock frequency selection bit to “1”, port
P4
0
becomes the frequency of f(X
IN
)/2 and port P4
1
becomes the
frequency of f(X
IN
)/10. At this time, the output pulses of both ports
P4
0
and P4
1
have duty ratio of 50%.
Fig. 35 Clock output function block diagram
Fig. 34 Structure of clock output control register
P4
0
clock output control bit
0 : I/O port
1 : Clock output
P4
1
clock output control bit
0 : I/O port
1 : Clock output
Output clock frequency selection bit
0 : P4
0
←
f(X
IN
), P4
1
←
f(X
IN
)/5
1 : P4
0
←
f(X
IN
)/2, P4
1
←
f(X
IN
)/10
Not used (return “0” when read)
Clock output control register
(TCON : address 002A
16
)
b7
b0
P4
0
1/2
P4
0
direction register
P4
0
clock output
control bit
“0”
“1”
P4
0
port latch
“0”
“1”
Output clock
frequency
selection bit
X
IN
P4
1
1/2
P4
1
direction register
P4
1
clock output
control bit
“0”
“1”
P4
1
port latch
“0”
“1” Output clock
frequency
selection bit
1/5
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