參數(shù)資料
型號(hào)： M38259EFGP
廠商： Mitsubishi Electric Corporation
英文描述： Quadruple Bus Buffer Gate With 3-State Outputs 14-SOIC -40 to 85
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 14/70頁
文件大?。?/td> 607K
代理商： M38259EFGP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
14
I/O PORTS
Direction Registers
The 3825 group has 43 programmable I/O pins arranged in seven
I/O ports (ports P1
6
, P1
7
P2, P4–P6, P7
1
–P7
7
, P8
0
and P8
1
). The
I/O ports have direction registers which determine the input/output
direction of each individual pin. (Ports P1
6
and P1
7
are shared
with bits 6 and 7 of the port P1 output control register). Each bit in
a direction register corresponds to one pin, and each pin can be
set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Port P1 Output Control Register
Bit 0 of the port P1 output control register (address 0003
16
) en-
ables control of the output of ports P1
0
to P1
5
.
When the bit is set to “1”, the port output function is valid.
In this case, setting of the PULL register A to ports P1
0
to P1
5
is
invalid.
When resetting, bit 0 of the port P1 output control register is set to
“0” (the port output function is invalid.)
Pull-up/Pull-down Control
By setting the PULL register A (address 0016
16
) or the PULL reg-
ister B (address 0017
16
), ports P0 to P8 except P7
0
can control ei-
ther pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports. (except for ports
P0 and P3).
Ports P0 and P3 share the port output control function with bit 0 of
the PULL register A. When set to “1”, the port output function is in-
valid (Pull-down is valid).
When set to “0”, the port output function is valid (Pull-down is in-
valid).
The PULL register A setting is invalid for pins set to segment out-
put with the segment output enable register.
Fig. 11 Structure of PULL register A and PULL register B
P0,
P1
0
–P1
5
, P3 pull-down
(shared with P0 and P3 output
control : refer to the text)
P1
6
–P1
7
pull-up
P2
0
–P2
7
pull-up
P8
0
, P8
1
pull-up
P4
0
–P4
3
pull-up
P4
4
–P4
7
pull-up
Not used (return “0” when read)
PULL register A
(PULLA : address 0016
16
)
b7
b0
P5
0
–P5
3
pull-up
P5
4
–P5
7
pull-up
P6
0
–P6
3
pull-up
P6
4
–P6
7
pull-up
P7
1
–P7
3
pull-up
P7
4
–P7
7
pull-up
Not used (return “0” when read)
0 : Disable
1 : Enable
PULL register B
(PULLB : address 0017
16
)
b7
b0
Note :
The contents of PULL register A and PULL register B
do not affect ports programmed as the output port.
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