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參數(shù)資料
| 型號(hào)： | M38258MCM |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Quadruple Bus Buffer Gate With 3-State Outputs 14-SOIC -40 to 85 |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 49/70頁(yè) |
| 文件大?。?/td> | 607K |
| 代理商： | M38258MCM |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
49
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Note :
When f(X
IN
) = 8 MHz and bit 6 of address 001A
16
is “1” (Clock synchronous).
Divide this value by four when f(X
IN
) = 8 MHz and bit 6 of address 001A
16
is “0” (UART).
Reset input “L” pulse width
Main clock input cycle time (X
IN
input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
to INT
3
input “H” pulse width
INT
0
to INT
3
input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
t
w(RESET)
t
c(X
IN
)
t
wH(X
IN
)
t
wL(X
IN
)
t
c(CNTR)
t
wH(CNTR)
t
wL(CNTR)
t
wH(INT)
t
wL(INT)
t
c(S
CLK
)
t
wH(S
CLK
)
t
wL(S
CLK
)
t
su(R
X
D–S
CLK
)
t
h(S
CLK
–R
X
D)
Symbol
Parameter
Limits
Typ.
Min.
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Max.
Table 18. Timing requirements 1
(V
CC
= 4.0 to 5.5 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted.)
2
125
45
40
500/
(V
CC
–2)
250/
(V
CC
–2)–20
250/
(V
CC
–2)–20
230
230
2000
950
950
400
200
Reset input “L” pulse width
Main clock input cycle time (X
IN
input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input “H” pulse width
CNTR
0
, CNTR
1
input “L” pulse width
INT
0
to INT
3
input “H” pulse width
INT
0
to INT
3
input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
Serial I/O input hold time
t
w(RESET)
t
c(X
IN
)
t
wH(X
IN
)
t
wL(X
IN
)
t
c(CNTR)
t
wH(CNTR)
t
wL(CNTR)
t
wH(INT)
t
wL(INT)
t
c(S
CLK
)
t
wH(S
CLK
)
t
wL(S
CLK
)
t
su(R
X
D–S
CLK
)
t
h(S
CLK
–R
X
D)
Symbol
Parameter
Limits
Typ.
Min.
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Max.
Note:
When f(X
IN
) = 8 MHz and bit 6 of address 001A
16
is “1” (Clock synchronous).
Divide this value by four when f(X
IN
) = 8 MHz and bit 6 of address 001A
16
is “0” (UART).
Table 19. Timing requirements 2
(V
CC
= 2.5 to 4.0 V, V
SS =
0 V, T
a
= –20 to 85
°
C, unless otherwise noted.)
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