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| 型號： | M3823AGF-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 19/76頁 |
| 文件大小： | 896K |
| 代理商： | M3823AGF-XXXHP |
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Rev.2.02
Jun 19, 2007
page 26 of 73
REJ03B0146-0202
3823 Group
Interrupt Request Generation, Acceptance,
and Handling
Interrupts have the following three phases.
(i) Interrupt Request Generation
An interrupt request is generated by an interrupt source (ex-
ternal interrupt signal input, timer underflow, etc.) and the
corresponding request bit is set to “1”.
(ii) Interrupt Request Acceptance
Based on the interrupt acceptance timing in each instruction
cycle, the interrupt control circuit determines acceptance con-
ditions (interrupt request bit, interrupt enable bit, and interrupt
disable flag) and interrupt priority levels for accepting interrupt
requests. When two or more interrupt requests are generated
simultaneously, the highest priority interrupt is accepted. The
value of interrupt request bit for an unaccepted interrupt re-
mains the same and acceptance is determined at the next
interrupt acceptance timing point.
(iii) Handling of Accepted Interrupt Request
The accepted interrupt request is processed.
Figure 18 shows the time up to execution in the interrupt process-
ing routine, and Figure 19 shows the interrupt sequence.
Figure 20 shows the timing of interrupt request generation, inter-
rupt request bit, and interrupt request acceptance.
Interrupt Handling Execution
When interrupt handling is executed, the following operations are
performed automatically.
(1) Once the currently executing instruction is completed, an inter-
rupt request is accepted.
(2) The contents of the program counters and the processor status
register at this point are pushed onto the stack area in order
from 1 to 3.
1. High-order bits of program counter (PCH)
2. Low-order bits of program counter (PCL)
3. Processor status register (PS)
(3) Concurrently with the push operation, the jump address of the
corresponding interrupt (the start address of the interrupt pro-
cessing routine) is transferred from the interrupt vector to the
program counter.
(4) The interrupt request bit for the corresponding interrupt is set
to “0”. Also, the interrupt disable flag is set to “1” and multiple
interrupts are disabled.
(5) The interrupt routine is executed.
(6) When the RTI instruction is executed, the contents of the reg-
isters pushed onto the stack area are popped off in the order
from 3 to 1. Then, the routine that was before running interrupt
processing resumes.
As described above, it is necessary to set the stack pointer and
the jump address in the vector area corresponding to each inter-
rupt to execute the interrupt processing routine.
■Notes
The interrupt request bit may be set to “1” in the following cases.
When setting the external interrupt active edge
Related registers: Interrupt edge selection register
(address 003A16)
Timer X mode register (address 002716)
Timer Y mode register (address 002816)
If it is not necessary to generate an interrupt synchronized with
these settings, take the following sequence.
(1) Set the corresponding enable bit to “0” (disabled).
(2) Set the interrupt edge selection bit (the active edge switch
bit) or the interrupt source bit.
(3) Set the corresponding interrupt request bit to “0” after one or
more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
Fig. 18 Time up to execution in interrupt routine
Fig. 19 Interrupt sequence
Main routine
Interrupt handling
routine
Interrupt request
generated
Interrupt request
acceptance
Interrupt routine
starts
Interrupt sequence
7 cycles
7 to 23 cycles
* When executing DIV instruction
Stack push and
Vector fetch
0 to 16 cycles
*
φ
SYNC
RD
WR
Address bus
Data bus
PC
Not used
S,SPS
S-1,SPS S-2,SPS
BL
BH
AL,AH
PCH
PCL
PS
AL
AH
SYNC :CPU operation code fetch cycle
(This is an internal signal that cannot be observed from the external unit.)
BL, BH: Vector address of each interrupt
AL, AH: Jump destination address of each interrupt
SPS
: “0016” or “0116”
([SPS] is a page selected by the stack page selection bit of CPU mode register.)
Push onto stack
Vector fetch
Execute interrupt
routine
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