參數(shù)資料
型號(hào)： M38235G6-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 19/64頁
文件大?。?/td> 922K
代理商： M38235G6-XXXFP
Rev.2.02
Jun 19, 2007
page 24 of 73
REJ03B0146-0202
3823 Group
Fig. 16 Interrupt control diagram
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
interrupt request
Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor sta-
tus register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is set
to “0”, acceptance of interrupt requests is enabled. This flag is set
to “1” with the SET instruction and set to “0” with the CLI instruc-
tion.
When an interrupt request is accepted, the contents of the proces-
sor status register are pushed onto the stack while the interrupt
disable flag remaines set to “0”. Subsequently, this flag is auto-
matically set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI instruc-
tion within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
Interrupt Request Bits
Once an interrupt request is generated, the corresponding inter-
rupt request bit is set to “1” and remaines “1” until the request is
accepted. When the request is accepted, this bit is automatically
set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
Interrupt Enable Bits
The interrupt enable bits control the acceptance of the corre-
sponding interrupt requests. When an interrupt enable bit is set to
“0”, the acceptance of the corresponding interrupt request is dis-
abled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Interrupt Source Selection
The following combinations can be selected by the interrupt
source selection bit of the AD control register (bit 6 of the address
003916).
ADT or A/D conversion (refer Table 9)
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