參數(shù)資料
型號(hào)： M38233G5-XXXHP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 60/76頁(yè)
文件大?。?/td> 896K
代理商： M38233G5-XXXHP
Rev.2.02 Jun 19, 2007 page 60 of 73
REJ03B0146-0202
3823 Group
Countermeasures against noise
(1) Shortest wiring length
Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin
as short as possible. Especially, connect a capacitor across the
RESET pin and the V
SS
pin with the shortest possible wiring
(within 20mm).
●
Reason
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is com-
pletely initialized. This may cause a program runaway.
(2) Connection of bypass capacitor across V
SS
line and V
CC
line
In order to stabilize the system operation and avoid the latch-up,
connect an approximately 0.1
μ
F bypass capacitor across the V
SS
line and the V
CC
line as follows:
Connect a bypass capacitor across the V
SS
pin and the V
CC
pin
at equal length.
Connect a bypass capacitor across the V
SS
pin and the V
CC
pin
with the shortest possible wiring.
Use lines with a larger diameter than other signal lines for V
SS
line and V
CC
line.
Connect the power source wiring via a bypass capacitor to the
V
SS
pin and the V
CC
pin.
Wiring for clock input/output pins
Make the length of wiring which is connected to clock I/O pins
as short as possible.
Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
V
SS
pin of a microcomputer as short as possible.
Separate the V
SS
pattern only for oscillation from other V
SS
patterns.
●
Reason
If noise enters clock I/O pins, clock waveforms may be de-
formed. This may cause a program failure or program runaway.
Also, if a potential difference is caused by the noise between
the V
SS
level of a microcomputer and the V
SS
level of an oscil-
lator, the correct clock will not be input in the microcomputer.
RESET
Reset
circuit
Noise
V
SS
V
SS
Reset
circuit
V
SS
RESET
V
SS
N.G.
O.K.
Noise
X
IN
X
OUT
V
SS
X
IN
X
OUT
V
SS
N.G.
O.K.
V
SS
V
CC
V
SS
V
CC
N.G.
O.K.
Fig. 63 Wiring for clock I/O pins
Fig. 62 Wiring for the RESET pin
Fig. 64 Bypass capacitor across the V
SS
line and the V
CC
line
相關(guān)PDF資料
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M38233G6-XXXHP 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
M38233G7-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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