參數(shù)資料
    型號(hào)： M38232G6-XXXFP
    廠商： Renesas Technology Corp.
    英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
    中文描述： 單芯片8位CMOS微機(jī)
    文件頁(yè)數(shù)： 13/76頁(yè)
    文件大小： 896K
    代理商： M38232G6-XXXFP
    Rev.2.02 Jun 19, 2007 page 13 of 73
    REJ03B0146-0202
    3823 Group
    [CPU Mode Register (CPUM)] 003B
    16
    The CPU mode register contains the stack page selection bit and
    the internal system clock selection bit.
    The CPU mode register is allocated at address 003B
    16
    .
    Fig. 8 Structure of CPU mode register
    Not available
    Processor mode bits
    b1 b0
    0 0 : Single-chip mode
    0 1 :
    1 0 :
    1 1 :
    Stack page selection bit
    0 : 0 page
    1 : 1 page
    Not used (returns “1” when read)
    (Do not write “0” to this bit)
    Port X
    C
    switch bit
    (Note 1)
    0 : I/O port function (stop oscillating)
    1 : X
    CIN
    –X
    COUT
    oscillating function
    Main clock (X
    IN
    –
    X
    OUT
    ) stop bit
    (Note 2)
    0 : Oscillating
    1 : Stopped
    Main clock division ratio selection bit
    0 : f(X
    IN
    )/2 (frequency/2 mode), or
    f(X
    IN
    )/4 (frequency/4 mode)
    (Note 3)
    1 : f(X
    IN
    )/8 (frequency/8 mode)
    Internal system clock selection bit
    0 : X
    IN
    –X
    OUT
    selected (frequency/2/4/8 mode)
    1 : X
    CIN
    –X
    COUT,
    or on-chip oscillator selected (low-speed mode)
    (Note 4)
    CPU mode register
    (CPUM (CM) : address 003B
    16
    )
    b7
    b0
    Note 1:
    In low speed mode (X
    CIN
    is selected as the system clock
    φ
    ), X
    CIN
    -X
    COUT
    oscillation does not stop even if the port X
    C
    switch bit is set to "0".
    2:
    In frequency/2/4/8 mode, X
    IN
    -X
    OUT
    oscillation does not stop even if the main clock (X
    IN
    -X
    OUT
    ) stop bit is set to "1".
    3:
    When the system clock
    φ
    is divided by 4 of f(X
    IN
    ), set the bit 6 in the CPU mode register to “0” after setting the bit 1
    in the CPU mode extension register to “1”.
    4:
    When using the on-chip oscillator in low-speed mode, set the bit 7 in the CPU mode register to “1” after setting the
    bit 0 in the CPU mode extension register to “1”.
    [CPU Mode Extension Register (EXPCM)] 002B
    16
    f(X
    IN
    ) divided by 4 for the system clock f and the on-chip oscillator
    for the system clock f in low-speed mode can be selected by set-
    ting the CPU mode extension register. When the system clock f is
    divided by 4 of f(X
    IN
    ), set the bit 6 in the CPU mode register to “0”
    after setting the bit 1 in the CPU mode extension register to “1”.
    When using the on-chip oscillator in low-speed mode, set the bit 7
    in the CPU mode register to “1” after setting the bit 0 in the CPU
    mode extension register to “1”.
    Fig. 9 Structure of CPU mode extension register
    On-chip oscillator control bit
    0 : On-chip oscillator not used
    (On -chip oscillator sotpping)
    1 : On-chip oscillator used
    (Note 1)
    (On -chip oscillator oscillating)
    Frequency/4 mode control bit
    (Note 2)
    0 : Frequency/2 mode
    φ
    = f(X
    IN
    )/2
    1 : Frequency/4 mode
    φ
    = f(X
    IN
    )/4
    Not used (returns “0” when read)
    (Do not write “1” to this bit)
    CPU mode extension register
    (EXPCM : address 002B
    16
    )
    b7
    b0
    1 :
    The on-chip oscillator is selected for the operation clock in low-speed mod regardless
    of X
    CIN
    -X
    COUT
    .
    2
    : Valid only when the main clock division ratio selection bit (bit 6 in the CPU mode
    register) is set to "0".
    When "1" (frequency/8 mode) is selected for the main clock division ratio selection bit or
    when the internal system clock selection bit is set to 1, set "0" to the frequency/4 mode
    control bit.
    Note
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