參數(shù)資料
型號(hào)： M38231GE-XXXFP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 23/76頁(yè)
文件大?。?/td> 896K
代理商： M38231GE-XXXFP
Rev.2.02 Jun 19, 2007 page 23 of 73
REJ03B0146-0202
3823 Group
INTERRUPTS
The 3823 group interrupts are vector interrupts with a fixed prior-
ity scheme, and generated by 16 sources among 17 sources: 8
external, 8 internal, and 1 software.
The interrupt sources, vector addresses
(1)
, and interrupt priority
are shown in Table 9.
Each interrupt except the BRK instruction interrupt has the inter-
rupt request bit and the interrupt enable bit. These bits and the
interrupt disable flag (I flag) control the acceptance of interrupt re-
quests. Figure 16 shows an interrupt control diagram.
Notes1:
Vector addresses contain interrupt jump destination addresses.
2:
Reset function in the same way as an interrupt with the highest priority.
Table 9 Interrupt vector addresses and priority
Remarks
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT
0
input
At detection of either rising or
falling edge of INT
1
input
At completion of serial interface
data reception
At completion of serial interface
transmit shift or when transmis-
sion buffer is empty
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR
0
input
At detection of either rising or
falling edge of CNTR
1
input
At timer 1 underflow
At detection of either rising or
falling edge of INT
2
input
At detection of either rising or
falling edge of INT
3
input
At falling of conjunction of input
level for port P2 (at input mode)
At falling of ADT input
Interrupt Source
Low
FFFC
16
FFFA
16
High
FFFD
16
FFFB
16
Priority
Vector Addresses
(Note 1)
Reset
(Note 2)
INT
0
INT
1
Serial I/O
reception
Serial I/O
transmission
Timer X
Timer Y
Timer 2
Timer 3
CNTR
0
CNTR
1
Timer 1
INT
2
INT
3
Key input
(Key-on wake-up)
ADT
A/D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
At completion of A/D conversion
At BRK instruction execution
Non-maskable
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial interface is se-
lected
Valid when serial interface is se-
lected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(Valid at falling)
Valid when ADT interrupt is se-
lected, External interrupt
(Valid at falling)
Valid when A/D interrupt is se-
lected
Non-maskable software interrupt
An interrupt requests is accepted when all of the following
conditions are satisfied:
Interrupt disable flag.................................“0”
Interrupt disable request bit .....................“1”
Interrupt enable bit................................... “1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
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