參數(shù)資料
型號： M38223E4HP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 39/46頁
文件大?。?/td> 910K
代理商： M38223E4HP
74
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
TDI, ADC7 – Port F, Bit 7
ADC7, Analog to Digital Converter, Channel 7.
TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains).
When the JTAG interface is enabled, this pin can not be used as an I/O pin.
TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6.
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface
is enabled, this pin can not be used as an I/O pin. In TAP states that shift out data, the TDO pin drives actively. In
other states the pin is pulled high.
TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, Channel 5.
TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state machine. When the
JTAG interface is enabled, this pin can not be used as an I/O pin.
TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4.
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can
not be used as an I/O pin.
ADC3 - ADC0 – Port F, Bit 3:0
Analog to Digital Converter, Channel 3-0.
Table 14-11. Port F pins alternate functions.
Port pin
Alternate function
PF7
ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)
PF6
ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)
PF5
ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)
PF4
ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)
PF3
ADC3 (ADC input channel 3)
PF2
ADC2 (ADC input channel 2)
PF1
ADC1 (ADC input channel 1)
PF0
ADC0 (ADC input channel 0)
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