參數(shù)資料
型號： M38223E4FS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CQCC80
封裝： 0.80 MM PITCH, CERAMIC, LCC-80
文件頁數(shù)： 38/46頁
文件大?。?/td> 910K
代理商： M38223E4FS
73
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Table 14-9 and Table 14-10 relates the alternate functions of Port E to the overriding signals shown in Figure 14-5
Note:
1. CKOUT is one if the CKOUT fuse is programmed.
Note:
14.3.4
Alternate functions of Port F
The Port F has an alternate function as analog input for the ADC as shown in Table 14-11 on page 74. If some Port
F pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This
might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI),
PF5(TMS) and PF4(TCK) will be activated even if a reset occurs.
Table 14-9.
Overriding signals for alternate functions PE7:PE4.
Signal name
PE7/PCINT7
PE6/DO/PCINT6
PE5/DI/SDA/PCINT5
PE4/USCK/SCL/PCINT4
PUOE
0
USI_TWO-WIRE
PUOV
0
DDOE
CKOUT(1)
0USI_TWO-WIRE
USI_TWO-WIRE
DDOV
1
0
(SDA + PORTE5) DDE5
(USI_SCL_HOLD PORTE4) +
DDE4
PVOE
CKOUT(1)
USI_THREE-WIRE
USI_TWO-WIRE DDE5
USI_TWO-WIRE DDE4
PVOV
clkI/O
DO
0
PTOE
–
0
USITC
DIEOE
PCINT7 PCIE0
PCINT6 PCIE0
(PCINT5 PCIE0) + USISIE
(PCINT4 PCIE0) + USISIE
DIEOV
1
DI
PCINT7 INPUT
PCINT6 INPUT
DI/SDA INPUT
PCINT5 INPUT
USCKL/SCL INPUT
PCINT4 INPUT
AIO
–
Table 14-10. Overriding signals for alternate functions in PE3:PE0.
Signal name
PE3/AIN1/PCINT3
PE2/XCK/AIN0/PCINT2
PE1/TXD/PCINT1
PE0/RXD/PCINT0
PUOE
0
TXENn
RXENn
PUOV
0
PORTE0 PUD
DDOE
0
TXENn
RXENn
DDOV
0
1
0
PVOE
0
XCK OUTPUT ENABLE
TXENn
0
PVOV
0
XCK
TXD
0
PTOE
–
DIEOE
(PCINT3 PCIE0) + AIN1D (1)
(PCINT2 PCIE0) + AIN0D (1)
PCINT1 PCIE0
PCINT0 PCIE0
DIEOV
PCINT3 PCIE0
PCINT2 PCIE0
1
DI
PCINT3 INPUT
XCK/PCINT2 INPUT
PCINT1 INPUT
RXD/PCINT0 INPUT
AIO
AIN1 INPUT
AIN0 INPUT
–
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