![](http://datasheet.mmic.net.cn/30000/M38223E4-XXXHP_datasheet_2360327/M38223E4-XXXHP_155.png)
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3822 GROUP USER’S MANUAL
2.4 Timer 1, timer 2, and timer 3
APPLICATION
2.4.2 Related registers
Figure 2.4.5 shows memory allocation of timer-related registers. Each of these registers is described
below.
Fig. 2.4.5 Memory allocation of timer-related registers
Address
Timer 123 mode register (T123M)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
002516
002616
002416
003C16
003D16
003E16
003F16
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
002916