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參數(shù)資料
| 型號： | M38207E8FS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 4 MHz, MICROCONTROLLER, CQCC80 |
| 封裝： | 0.80 MM PITCH, CERAMIC, LCC-80 |
| 文件頁數(shù)： | 61/67頁 |
| 文件大?。?/td> | 1099K |
| 代理商： | M38207E8FS |
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63
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Measurement output pin
100pF
CMOS output
Note: When bit 4 of the UART
control register (address 001B 16) is “1”.
(N-channel open-drain output mode)
Measurement output pin
100pF
N-channel open-drain output (Note)
1k
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
140
30
0.2!tC(SCLK2)
40
30
Symbol
Parameter
Limits
Min.
ns
Unit
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85
°C, unless otherwise noted.)
tc(SCLK1)/2–30
–30
tc(SCLK2)/2–160
0
10
Typ.
Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
td(SCLK2–SOUT2)
tv(SCLK2–SOUT2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
SWITCHING CHARACTERISTICS 1 (Low Power Source Voltage Version)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
350
50
0.2!tC(SCLK2)
50
Symbol
Parameter
Limits
Min.
ns
Unit
(VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85
°C, unless otherwise noted.)
tc(SCLK1)/2–50
–30
tc(SCLK2)/2–240
0
20
Max.
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
td(SCLK2–SOUT2)
tv(SCLK2–SOUT2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Notes 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are excluded.
SWITCHING CHARACTERISTICS 2 (Low Power Source Voltage Version)
Typ.
Fig.41 Circuit for measuring output switching characteristics
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相關(guān)代理商/技術(shù)參數(shù) |
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| M38207E8GP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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| M38207M8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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