參數(shù)資料
型號: M38203M4LXXXHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80
封裝: 0.50 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 52/69頁
文件大?。?/td> 944K
代理商: M38203M4LXXXHP
Rev.4.01
Nov 14, 2003
page 56 of 136
3803/3804 Group
Serial I/O2
The serial I/O2 function can be used only for clock synchronous
serial I/O.
For clock synchronous serial I/O2, the transmitter and the receiver
must use the same clock. If the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
[Serial I/O2 Control Register (SIO2CON)]
001D16
The serial I/O2 control register contains eight bits which control
various serial I/O2 functions.
Fig. 45 Structure of serial I/O2 control register
Fig. 46 Block diagram of serial I/O2
Serial I/O2 control register
(SIO2CON : address 001D16)
b7
Internal synchronous clock selection bits
0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode)
1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 signal output
SRDY2 output enable bit
0: I/O port
1: SRDY2 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P51/SOUT2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
b0
b2 b1 b0
“1”
“0”
“1”
“0”
“1”
SRDY2
S
C
L
K
2
“0”
“1”
1/8
1/16
1/32
1/64
1/128
1/256
Data bus
Serial I/O2
interrupt request
Serial I/O2 port selection bit
Serial I/O counter 2 (3)
Serial I/O2 register (8)
Synchronization
circuit
Serial I/O2 port selection bit
Serial I/O2 synchronous
clock selection bit
SRDY2 output enable bit
External clock
Internal synchronous
clock selection bits
D
iv
id
e
r
P52/SCLK2
P51/SOUT2
P50/SIN2
P52 latch
P51 latch
P53 latch
P53/SRDY2
f(XIN)
(f(XCIN) in low-speed mode)
Address 001F16
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