參數(shù)資料
型號: M38203M2LXXXHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80
封裝: 0.50 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 19/67頁
文件大小: 1099K
代理商: M38203M2LXXXHP
25
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O1. A dedicated timer (baud rate generator)
is also provided for baud rate generation.
Clock Synchronous Serial I/O1 Mode
Clock synchronous serial I/O1 mode can be selected by setting
the mode selection bit of the serial I/O1 control register to “1”.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB (address 001816).
Fig. 15 Block diagram of clock synchronous serial I/O1
Fig. 16 Operation of clock synchronous serial I/O1 function
1/4
XIN
1/4
F/F
P46/SCLK1
Serial I/O1 status register
Serial I/O1 control register
P47/SRDY1
P44/RXD
P45/TXD
f(XIN)
Receive buffer register (RB)
Address 001816
Receive shift register
Receive buffer full flag (RBF)
Serial I/O receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O1 synchronization
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
BRG count source selection bit
Clock control circuit
Falling-edge detector
Data bus
Address 001816
Shift clock
Transmit shift register shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Serial I/O transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001916
Data bus
Address 001A16
Transmit shift register
Transmit buffer register (TB)
D7
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Write signal to receive/transmit
buffer register (address 001816)
Overrun error (OE)
detection
Notes 1 : The serial I/O1 transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1)
or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TxD pin.
3 : The serial I/O1 receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal SRDY1
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