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參數(shù)資料
| 型號： | M38196MF-XXXFS |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 39/60頁 |
| 文件大小： | 664K |
| 代理商： | M38196MF-XXXFS |
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39
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
G n
G n-1
G n-2
G 1
T
scan
disp
Segment
output
FLD digit interrupt occurs
at the rising edge of each digit
FLD blanking interrupt occurs
at the falling edge of the last digit
Segment setting by software
T
off
T
disp
Digit
Segment
G
Timing Setting
The digit time (T
disp
) can be set with the FLDC mode register 2
(address 0037
16
). The T
scan
and digit/segment OFF time (T
off
)
can be set with the FLDC mode register 1 (address 0036
16
).
Note that flickering will occur if the repetition frequency (1/
(T
disp
number of digits + T
scan
)) is an integral multiple of the
digit timing T
disp
.
G
FLD Automatic Display Start
To perform FLD automatic display, set the following registers.
Port P0 segment/digit switch register
Port P2 digit/port switch register
Port P8 segment/port switch register
Port PA segment/port switch register
FLDC mode register 1
FLDC mode register 2
FLD data pointer
Automatic display mode is selected by writing “1” to the bit 0 of
the FLDC mode register 2 (address 0037
16
), and the auto-
matic display is started by writing “1” to the bit 1.
During automatic display bit 1 of the FLDC mode register 2 al-
ways keeps “1”, automatic display can be interrupted by writing
“0” to the bit 1.
G
Key-scan
If key-scan is performed with the segment during the key-scan
blanking period T
scan
, take the following sequence:
1. Write “0” to the bit 0 (automatic display control bit) of the
FLDC mode register 2 (address 0037
16
).
2. Set the port corresponding to the segment for key-scan to
the output port.
3. Perform the key-scan.
4. After the key-scan is performed, write “1” (automatic display
mode) to the bit 0 of FLDC mode register 2 (address
0037
16
).
Note on performance of key-scan in the above 1 to 4 sequence.
1. Do not write “0” to the bit 1 of FLDC mode register 2 (ad-
dress 0037
16
).
2. Do not write “1” to the port corresponding to the digit.
Fig. KA-7 FLDC timing
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