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| 型號(hào)： | M38039MCH-XXXSP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | 0.750 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-64 |
| 文件頁(yè)數(shù)： | 20/117頁(yè) |
| 文件大?。?/td> | 1873K |
| 代理商： | M38039MCH-XXXSP |
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REVISION HISTORY
3803 Group (Spec.H) Data Sheet
Rev.
Date
Description
Page
Summary
3.03
Jun.17, 2005
5
Fig.3, Table 5 Package name revised.
9
“Packages” Package name revised.
74 to 85
Fig.74 to Fig.77 Package name revised.
89
Table 17 is partly revised.
106 to 108 PACKAGE OUTLINE revised.
3.10
Nov.14, 2005
-
Bit name revised: STP instruction disable bit → STP instruction function selection
bit
20
Fig.15 Port block diagram (18) Port P56 revised.
61
Watchdog Timer Operations revised.
Bit 6 of Watchdog Timer Control Register added.
Fig.55: Block diagram of Watchdog timer revised.
Fig.56: Structure of Watchdog timer control register revised.
Bit name and its description revised. (Bit function is not changed.)
→ STP instruction function selection bit
0 : Entering stop mode by execution of STP instruction
1 : Internal reset by execution of STP instruction
88
Flash Memory Version revised.
Fig.80: Wiring for the CNVSS pin added.
106 to 108 PACKAGE OUTLINE revised.
109 to 116 Appendix added.
3.11
Apr.5, 2006
1, 5
Table 1, Table 5, Fig.3; M38037M8H-XXXWG deleted.
7
Table 6 Functions revised.
9
Packages; “LGA” → “FLGA”
13
[CPU Mode Register (CPUM)] “The CPU mode register .... selection bit, etc.” →
“The CPU mode register ....selection bit, the internal system clock control bits, etc.”
15
MEMORY <Note> added.
17
I/O PORTS; “By setting the port P0 pull-up control register....programmed as the
output ports.” added.
Table 9 Input/Output added.
19
Fig.14 Port P40, P41 revised.
44, 52
[Serial I/O1 Status Register (SIO1STS)] “If there is an error,....the transmit buffer
empty flag (bit 0) become “1”.” revised.
56
Data Setting “count source selection bit = “0”” added.
Fig.47 “XIN or XCIN” → “XIN (XCIN at low-speed mode)
57
Fig.48; “f(XCIN) at low-speed mode”, “f(XCIN)/2 at low-speed mode” added.
<Notes> added.
64
Frequency Control; (4) Low power dissipation mode added.
Oscillation Control; (2) Wait mode, <Notes> added.
86, 87
Fig.78, Fig.79 added.
NOTES ON PROGRAMMING, NOTES ON USAGE deleted.
→ Included in NOTES
96, 97
Table 24, Table 27; f(XIN)
Conditions: “VCC” → “VCC = VREF”
Limits Max.:
“
”
→
“
”
24
VCC
60
–
×
() 1.05
×
3
-----------------------------------------------------------
24.6
VCC
62.7
–
×
() 1.05
×
3
---------------------------------------------------------------------
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M38039FFSP | 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PDIP64 |
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| M38037M8H-XXXWG | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64 |
| M38039FFSP | 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PDIP64 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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