參數(shù)資料
型號： M38039FFSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-64
文件頁數(shù)： 19/117頁
文件大?。?/td> 1873K
代理商： M38039FFSP
(2/3)
REVISION HISTORY
3803 Group (Spec.H) Data Sheet
Rev.
Date
Description
Page
Summary
3.01 Jun.25, 2004 61
61
63
65
69
70
80
86
87
88
97
98
99
101
Explanations of “RESET CIRCUIT” are partly revised.
Figure 56 Reset circuit example is partly revised.
Explanations of “(1) Stop mode” of “Oscillation control” are partly added.
Figure 56 Reset circuit example is partly revied.
Explanations of “Outline Performance” are partly revised.
Figure 64 Structure of flash memory control register 0 is partly revised.
Figure 66 is partly revised.
Table 11 is partly revised.
Figure 67 is partly revised.
P46 of Table 15 is revised.
“NOTES ON PROGRAMMING” is added.
“DATA REQUIRED FOR MASK ORDERS” is added.
Note of Table 16 is partly revised.
Table 26 A/D converter characteristics (Mask ROM version) is partly revised.
Table 27 D/A converter characteristics (Mask ROM version) is partly revised.
Table 29 A/D converter characteristics (Flash memory version) is partly revised.
Table 30 D/A converter characteristics (Flash memory version) is partly revised.
Table 31 Power source circuit timing characteristics (Flash memory version) is
added.
____________
tw(RESET) of Table 32 is revised.
Table 33 and Table 34 of Rev.3.00 are eliminated.
3.02 Nov.05, 2004 1
1,2,5,8,9
9
35
62
64
65
66
77
80
95
100,101
102,103
104
105
108
Memory size
ROM....16 K to 32 K bytes
→ 16 K to 60 K bytes
RAM....640 to 1024 bytes
→ 640 to 2048 bytes
WG version is added.
Fig.6 is partly eliminated.
(5) Pulse width measurement mode is partly revised.
Fig.58 is partly revised.
CLOCK GENERATING CIRCUIT is partly revised.
Fig.60 is partly revised.
Note 4 of Fig.62 is added.
Functions To Inhibit Rewriting Flash Memory Version is partly added.
Standard serial I/O Mode is partly revised.
Outline Performance (Standard Serial I/O Mode) is eliminated.
Table 23 Electrical characteristics (1)
“VOL “L” output voltage P20–P27” is added.
Table 33 Timing requirements (1), Table 34 Timing requirements (2)
(In high-speed mode) is deleted.
Mask ROM versoin: Vcc = 1.8 to 5.5V
→ Vcc = 2.0 to 5.5V
Table 35 Switching characteristics (1), Table 36 Switching characteristics (2) are
added.
Fig.80 Circuit for measuring output switching characteristics (1),
Fig.81 Circuit for measuring output switching characteristics (2) are added.
Fig.82 Timing diagram (in single-chip mode) is revised.
PACKAGE OUTLINE 64F0G is added.
3.03 Jun.17, 2005 All pages Delete the following: “Under development”.
1
●Packages, Table 1 Package name revised.
2
●Packages, Table 2 Package name revised.
3
Fig.1, Table 3 Package name revised.
4
Fig.2, Table 4 Package name revised.
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